/dports/cad/tkgate/tkgate-2.1/locale/es/examples/ex5/ |
H A D | menagerie.v | 544 module REG4(B, _ENA, SB, CK, _ENB, DIN, _WA, _CLR, SA, A); 570 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 628 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w2)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 745 output _WA; //: /sn:0 {0}(693,754)(488,754){1} port 963 module ZREG4(CK, SB, _ENA, B, DIN, _ENB, _WA, _CLR, SA, A); 988 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 1043 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w19)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 1132 module REG16(DIN, SB, _ENA, SA, A, B, CK, _WA, _CLR, _ENB); 1166 input _WA; //: /sn:0 {0}(42,379)(277,379){1} port 1247 …REG4 RF2 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w26), ._ENB(w25), ._WA(_WA), .CK(CK), … [all …]
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/dports/cad/tkgate/tkgate-2.1/locale/ja/examples/ex5/ |
H A D | menagerie.v | 544 module REG4(B, _ENA, SB, CK, _ENB, DIN, _WA, _CLR, SA, A); 570 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 628 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w2)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 745 output _WA; //: /sn:0 {0}(693,754)(488,754){1} port 963 module ZREG4(CK, SB, _ENA, B, DIN, _ENB, _WA, _CLR, SA, A); 988 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 1043 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w19)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 1132 module REG16(DIN, SB, _ENA, SA, A, B, CK, _WA, _CLR, _ENB); 1166 input _WA; //: /sn:0 {0}(42,379)(277,379){1} port 1247 …REG4 RF2 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w26), ._ENB(w25), ._WA(_WA), .CK(CK), … [all …]
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/dports/cad/tkgate/tkgate-2.1/locale/it/examples/ex5/ |
H A D | menagerie.v | 547 module REG4(B, _ENA, SB, CK, _ENB, DIN, _WA, _CLR, SA, A); 573 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 631 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w2)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 748 output _WA; //: /sn:0 {0}(693,754)(488,754){1} port 966 module ZREG4(CK, SB, _ENA, B, DIN, _ENB, _WA, _CLR, SA, A); 991 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 1046 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w19)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 1135 module REG16(DIN, SB, _ENA, SA, A, B, CK, _WA, _CLR, _ENB); 1169 input _WA; //: /sn:0 {0}(42,379)(277,379){1} port 1250 …REG4 RF2 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w26), ._ENB(w25), ._WA(_WA), .CK(CK), … [all …]
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/dports/cad/tkgate/tkgate-2.1/locale/ru/examples/ex5/ |
H A D | menagerie.v | 547 module REG4(B, _ENA, SB, CK, _ENB, DIN, _WA, _CLR, SA, A); 573 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 631 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w2)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 748 output _WA; //: /sn:0 {0}(693,754)(488,754){1} port 960 module ZREG4(CK, SB, _ENA, B, DIN, _ENB, _WA, _CLR, SA, A); 985 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 1040 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w19)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 1129 module REG16(DIN, SB, _ENA, SA, A, B, CK, _WA, _CLR, _ENB); 1163 input _WA; //: /sn:0 {0}(42,379)(277,379){1} port 1244 …REG4 RF2 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w26), ._ENB(w25), ._WA(_WA), .CK(CK), … [all …]
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/dports/cad/tkgate/tkgate-2.1/locale/en/examples/ex5/ |
H A D | menagerie.v | 544 module REG4(B, _ENA, SB, CK, _ENB, DIN, _WA, _CLR, SA, A); 570 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 628 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w2)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 745 output _WA; //: /sn:0 {0}(693,754)(488,754){1} port 963 module ZREG4(CK, SB, _ENA, B, DIN, _ENB, _WA, _CLR, SA, A); 988 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 1043 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w19)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 1132 module REG16(DIN, SB, _ENA, SA, A, B, CK, _WA, _CLR, _ENB); 1166 input _WA; //: /sn:0 {0}(42,379)(277,379){1} port 1247 …REG4 RF2 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w26), ._ENB(w25), ._WA(_WA), .CK(CK), … [all …]
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/dports/cad/tkgate/tkgate-2.1/locale/pl/examples/ex5/ |
H A D | menagerie.v | 544 module REG4(B, _ENA, SB, CK, _ENB, DIN, _WA, _CLR, SA, A); 570 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 628 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w2)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 745 output _WA; //: /sn:0 {0}(693,754)(488,754){1} port 963 module ZREG4(CK, SB, _ENA, B, DIN, _ENB, _WA, _CLR, SA, A); 988 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 1043 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w19)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 1132 module REG16(DIN, SB, _ENA, SA, A, B, CK, _WA, _CLR, _ENB); 1166 input _WA; //: /sn:0 {0}(42,379)(277,379){1} port 1247 …REG4 RF2 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w26), ._ENB(w25), ._WA(_WA), .CK(CK), … [all …]
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/dports/cad/tkgate/tkgate-2.1/locale/uk/examples/ex5/ |
H A D | menagerie.v | 544 module REG4(B, _ENA, SB, CK, _ENB, DIN, _WA, _CLR, SA, A); 570 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 628 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w2)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 745 output _WA; //: /sn:0 {0}(693,754)(488,754){1} port 963 module ZREG4(CK, SB, _ENA, B, DIN, _ENB, _WA, _CLR, SA, A); 988 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 1043 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w19)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 1132 module REG16(DIN, SB, _ENA, SA, A, B, CK, _WA, _CLR, _ENB); 1166 input _WA; //: /sn:0 {0}(42,379)(277,379){1} port 1247 …REG4 RF2 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w26), ._ENB(w25), ._WA(_WA), .CK(CK), … [all …]
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/dports/cad/tkgate/tkgate-2.1/locale/cs/examples/ex5/ |
H A D | menagerie.v | 544 module REG4(B, _ENA, SB, CK, _ENB, DIN, _WA, _CLR, SA, A); 570 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 628 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w2)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 745 output _WA; //: /sn:0 {0}(693,754)(488,754){1} port 960 module ZREG4(CK, SB, _ENA, B, DIN, _ENB, _WA, _CLR, SA, A); 985 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 1040 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w19)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 1129 module REG16(DIN, SB, _ENA, SA, A, B, CK, _WA, _CLR, _ENB); 1163 input _WA; //: /sn:0 {0}(42,379)(277,379){1} port 1244 …REG4 RF2 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w26), ._ENB(w25), ._WA(_WA), .CK(CK), … [all …]
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/dports/cad/tkgate/tkgate-2.1/locale/de/examples/ex5/ |
H A D | menagerie.v | 545 module REG4(B, _ENA, SB, CK, _ENB, DIN, _WA, _CLR, SA, A); 571 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 629 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w2)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 746 output _WA; //: /sn:0 {0}(693,754)(488,754){1} port 962 module ZREG4(CK, SB, _ENA, B, DIN, _ENB, _WA, _CLR, SA, A); 987 input _WA; //: /sn:0 {0}(52,269)(91,269)(91,292)(104,292){1} port 1042 _GGOR2 #(6) g26 (.I0(_WA), .I1(_ENA), .Z(w19)); //: @(115,295) /sn:0 /w:[ 1 3 0 ] /eb:0 1131 module REG16(DIN, SB, _ENA, SA, A, B, CK, _WA, _CLR, _ENB); 1165 input _WA; //: /sn:0 {0}(42,379)(277,379){1} port 1246 …REG4 RF2 (.DIN(DIN), .SA(w50), .SB(w49), ._CLR(_CLR), ._ENA(w26), ._ENB(w25), ._WA(_WA), .CK(CK), … [all …]
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/dports/japanese/sj3-lib/sj3-2.0.1.20/kanakan/ |
H A D | fzkyomi.c | 272 (1<<5) + 1, _WA, L_YOUGEN, R_MIZEN5, 283 (1<<5) + 1, _WA, L_JIMAU, R_MIZEN5, 290 (1<<5) + 1, _WA, L_JYAU, R_MIZEN5, 372 (1<<5) + 1, _WA, L_TAMAU, R_MIZEN5, 400 (1<<5) + 1, _WA, L_TIMAU, R_MIZEN5, 407 (1<<5) + 1, _WA, L_TYAU, R_MIZEN5, 656 (1<<5) + 1, _WA, L_YOUGEN, R_MIZEN5,
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H A D | conjunc.c | 449 0x01, _WA, R_MIZEN5, 459 0x01, _WA, R_MIZEN5, 471 0x01, _WA, R_MIZEN5, 487 0x01, _WA, R_MIZEN5,
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/dports/japanese/sj3-lib/sj3-2.0.1.20/include/ |
H A D | sj_yomi.h | 192 #define _WA 0x9C macro
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/dports/lang/sdcc/sdcc-4.0.0/device/non-free/include/pic14/ |
H A D | pic16lf1902.h | 1488 #define _WA 0x10 macro
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H A D | pic16lf1903.h | 1488 #define _WA 0x10 macro
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H A D | pic16lf1906.h | 2010 #define _WA 0x10 macro
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H A D | pic16f913.h | 1805 #define _WA 0x10 macro
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H A D | pic16f916.h | 1805 #define _WA 0x10 macro
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H A D | pic16lf1904.h | 2229 #define _WA 0x10 macro
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H A D | pic16f914.h | 1939 #define _WA 0x10 macro
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H A D | pic16f917.h | 1939 #define _WA 0x10 macro
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/dports/lang/sdcc/sdcc-4.0.0/device/non-free/include/pic16/ |
H A D | pic18f67j90.h | 3398 #define _WA 0x10 macro
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H A D | pic18f86j72.h | 3398 #define _WA 0x10 macro
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H A D | pic18f67j93.h | 3441 #define _WA 0x10 macro
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H A D | pic18f64j90.h | 3429 #define _WA 0x10 macro
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/dports/devel/radare2/radare2-5.1.1/test/db/formats/mangling/ |
H A D | mangling | 163 CMDS="!rabin2 -D msvc ?var_wchar_t@@3_WA"
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