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Searched refs:____cacheline_aligned (Results 1 – 25 of 801) sorted by relevance

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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/crypto/ccree/
H A Dcc_aead.h51 u8 mac_buf[MAX_MAC_SIZE] ____cacheline_aligned;
52 u8 ctr_iv[AES_BLOCK_SIZE] ____cacheline_aligned;
55 u8 gcm_iv_inc1[AES_BLOCK_SIZE] ____cacheline_aligned;
56 u8 gcm_iv_inc2[AES_BLOCK_SIZE] ____cacheline_aligned;
57 u8 hkey[AES_BLOCK_SIZE] ____cacheline_aligned;
59 u8 len_a[GCM_BLOCK_LEN_SIZE] ____cacheline_aligned;
63 u8 ccm_config[CCM_CONFIG_BUF_SIZE] ____cacheline_aligned;
65 unsigned int hw_iv_size ____cacheline_aligned; member
H A Dcc_hash.h38 u8 buffers[2][CC_MAX_HASH_BLCK_SIZE] ____cacheline_aligned;
39 u8 digest_result_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
40 u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
41 u8 opad_digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
42 u8 digest_bytes_len[HASH_MAX_LEN_SIZE] ____cacheline_aligned;
43 struct async_gen_req_ctx gen_ctx ____cacheline_aligned; member
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/crypto/ccree/
H A Dcc_aead.h51 u8 mac_buf[MAX_MAC_SIZE] ____cacheline_aligned;
52 u8 ctr_iv[AES_BLOCK_SIZE] ____cacheline_aligned;
55 u8 gcm_iv_inc1[AES_BLOCK_SIZE] ____cacheline_aligned;
56 u8 gcm_iv_inc2[AES_BLOCK_SIZE] ____cacheline_aligned;
57 u8 hkey[AES_BLOCK_SIZE] ____cacheline_aligned;
59 u8 len_a[GCM_BLOCK_LEN_SIZE] ____cacheline_aligned;
63 u8 ccm_config[CCM_CONFIG_BUF_SIZE] ____cacheline_aligned;
65 unsigned int hw_iv_size ____cacheline_aligned; member
H A Dcc_hash.h38 u8 buffers[2][CC_MAX_HASH_BLCK_SIZE] ____cacheline_aligned;
39 u8 digest_result_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
40 u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
41 u8 opad_digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
42 u8 digest_bytes_len[HASH_MAX_LEN_SIZE] ____cacheline_aligned;
43 struct async_gen_req_ctx gen_ctx ____cacheline_aligned; member
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/crypto/ccree/
H A Dcc_aead.h51 u8 mac_buf[MAX_MAC_SIZE] ____cacheline_aligned;
52 u8 ctr_iv[AES_BLOCK_SIZE] ____cacheline_aligned;
55 u8 gcm_iv_inc1[AES_BLOCK_SIZE] ____cacheline_aligned;
56 u8 gcm_iv_inc2[AES_BLOCK_SIZE] ____cacheline_aligned;
57 u8 hkey[AES_BLOCK_SIZE] ____cacheline_aligned;
59 u8 len_a[GCM_BLOCK_LEN_SIZE] ____cacheline_aligned;
63 u8 ccm_config[CCM_CONFIG_BUF_SIZE] ____cacheline_aligned;
65 unsigned int hw_iv_size ____cacheline_aligned; member
H A Dcc_hash.h38 u8 buffers[2][CC_MAX_HASH_BLCK_SIZE] ____cacheline_aligned;
39 u8 digest_result_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
40 u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
41 u8 opad_digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
42 u8 digest_bytes_len[HASH_MAX_LEN_SIZE] ____cacheline_aligned;
43 struct async_gen_req_ctx gen_ctx ____cacheline_aligned; member
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/target/
H A Dtarget_core_pscsi.h28 } ____cacheline_aligned; variable
47 } ____cacheline_aligned; variable
58 } ____cacheline_aligned; variable
H A Dtarget_core_rd.h27 } ____cacheline_aligned; variable
50 } ____cacheline_aligned; variable
55 } ____cacheline_aligned; variable
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/target/
H A Dtarget_core_pscsi.h28 } ____cacheline_aligned; variable
47 } ____cacheline_aligned; variable
58 } ____cacheline_aligned; variable
H A Dtarget_core_rd.h27 } ____cacheline_aligned; variable
50 } ____cacheline_aligned; variable
55 } ____cacheline_aligned; variable
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/target/
H A Dtarget_core_pscsi.h28 } ____cacheline_aligned; variable
47 } ____cacheline_aligned; variable
58 } ____cacheline_aligned; variable
H A Dtarget_core_rd.h27 } ____cacheline_aligned; variable
50 } ____cacheline_aligned; variable
55 } ____cacheline_aligned; variable
/dports/multimedia/v4l_compat/linux-5.13-rc2/include/linux/
H A Dcache.h40 #ifndef ____cacheline_aligned
41 #define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES))) macro
46 #define ____cacheline_aligned_in_smp ____cacheline_aligned
/dports/multimedia/libv4l/linux-5.13-rc2/include/linux/
H A Dcache.h40 #ifndef ____cacheline_aligned
41 #define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES))) macro
46 #define ____cacheline_aligned_in_smp ____cacheline_aligned
/dports/multimedia/v4l-utils/linux-5.13-rc2/include/linux/
H A Dcache.h40 #ifndef ____cacheline_aligned
41 #define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES))) macro
46 #define ____cacheline_aligned_in_smp ____cacheline_aligned
/dports/multimedia/libv4l/linux-5.13-rc2/include/target/iscsi/
H A Discsi_target_stat.h37 } ____cacheline_aligned; variable
60 } ____cacheline_aligned; variable
67 } ____cacheline_aligned; variable
H A Discsi_target_core.h323 } ____cacheline_aligned; variable
332 } ____cacheline_aligned; variable
339 } ____cacheline_aligned; variable
350 } ____cacheline_aligned; variable
501 } ____cacheline_aligned; variable
609 } ____cacheline_aligned; variable
688 } ____cacheline_aligned; variable
714 } ____cacheline_aligned; variable
797 } ____cacheline_aligned; variable
839 } ____cacheline_aligned; variable
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/include/target/iscsi/
H A Discsi_target_stat.h37 } ____cacheline_aligned; variable
60 } ____cacheline_aligned; variable
67 } ____cacheline_aligned; variable
H A Discsi_target_core.h323 } ____cacheline_aligned; variable
332 } ____cacheline_aligned; variable
339 } ____cacheline_aligned; variable
350 } ____cacheline_aligned; variable
501 } ____cacheline_aligned; variable
609 } ____cacheline_aligned; variable
688 } ____cacheline_aligned; variable
714 } ____cacheline_aligned; variable
797 } ____cacheline_aligned; variable
839 } ____cacheline_aligned; variable
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/include/target/iscsi/
H A Discsi_target_stat.h37 } ____cacheline_aligned; variable
60 } ____cacheline_aligned; variable
67 } ____cacheline_aligned; variable
H A Discsi_target_core.h323 } ____cacheline_aligned; variable
332 } ____cacheline_aligned; variable
339 } ____cacheline_aligned; variable
350 } ____cacheline_aligned; variable
501 } ____cacheline_aligned; variable
609 } ____cacheline_aligned; variable
688 } ____cacheline_aligned; variable
714 } ____cacheline_aligned; variable
797 } ____cacheline_aligned; variable
839 } ____cacheline_aligned; variable
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/scsi/snic/
H A Dsnic.h306 ____cacheline_aligned spinlock_t io_req_lock[SNIC_IO_LOCKS];
309 ____cacheline_aligned spinlock_t spl_cmd_lock;
341 ____cacheline_aligned struct vnic_cq cq[SNIC_CQ_MAX];
344 ____cacheline_aligned struct vnic_wq wq[SNIC_WQ_MAX];
348 ____cacheline_aligned struct vnic_intr intr[SNIC_MSIX_INTR_MAX];
367 struct snic_trc trc ____cacheline_aligned; member
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/scsi/snic/
H A Dsnic.h306 ____cacheline_aligned spinlock_t io_req_lock[SNIC_IO_LOCKS];
309 ____cacheline_aligned spinlock_t spl_cmd_lock;
341 ____cacheline_aligned struct vnic_cq cq[SNIC_CQ_MAX];
344 ____cacheline_aligned struct vnic_wq wq[SNIC_WQ_MAX];
348 ____cacheline_aligned struct vnic_intr intr[SNIC_MSIX_INTR_MAX];
367 struct snic_trc trc ____cacheline_aligned; member
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/scsi/snic/
H A Dsnic.h306 ____cacheline_aligned spinlock_t io_req_lock[SNIC_IO_LOCKS];
309 ____cacheline_aligned spinlock_t spl_cmd_lock;
341 ____cacheline_aligned struct vnic_cq cq[SNIC_CQ_MAX];
344 ____cacheline_aligned struct vnic_wq wq[SNIC_WQ_MAX];
348 ____cacheline_aligned struct vnic_intr intr[SNIC_MSIX_INTR_MAX];
367 struct snic_trc trc ____cacheline_aligned; member
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/crypto/
H A Dtalitos.h96 atomic_t submit_count ____cacheline_aligned; member
99 spinlock_t head_lock ____cacheline_aligned; member
104 spinlock_t tail_lock ____cacheline_aligned; member
124 spinlock_t reg_lock ____cacheline_aligned; member
145 atomic_t last_chan ____cacheline_aligned; member

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