Searched refs:addDffe (Results 1 – 6 of 6) sorted by relevance
| /dports/cad/yosys/yosys-yosys-0.12/passes/pmgen/ |
| H A D | xilinx_srl.pmg | 226 //cell = module->addDffe(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 4);
302 …module->addDffe(NEW_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POL…
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| /dports/cad/yosys/yosys-yosys-0.12/kernel/ |
| H A D | ff.cc | 593 cell = module->addDffe(name, sig_clk, sig_ce, sig_d, sig_q, pol_clk, pol_ce); in emit()
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| H A D | mem.cc | 1133 module->addDffe(NEW_ID, rport.clk, rport.en, wport.data, wdata_q, rport.clk_polarity, true); in emulate_transparency()
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| H A D | rtlil.h | 1314 …RTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &…
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| H A D | rtlil.cc | 2677 RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLI… in addDffe() function in RTLIL::Module
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| /dports/cad/yosys/yosys-yosys-0.12/passes/memory/ |
| H A D | memory_bram.cc | 978 module->addDffe(NEW_ID, port.clk, port.en, addr_ok, addr_ok_q, port.clk_polarity); in replace_memory()
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