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Searched refs:addFf (Results 1 – 10 of 10) sorted by relevance

/dports/cad/yosys/yosys-yosys-0.12/passes/sat/
H A Dclk2fflogic.cc44 module->addFf(NEW_ID, sig, past_sig); in wrap_async_control()
110 module->addFf(NEW_ID, port.clk, past_clk); in execute()
125 module->addFf(NEW_ID, port.en, en_q); in execute()
128 module->addFf(NEW_ID, port.addr, addr_q); in execute()
131 module->addFf(NEW_ID, port.data, data_q); in execute()
175 module->addFf(NEW_ID, ff.sig_q, past_q); in execute()
189 module->addFf(NEW_ID, ff.sig_clk, past_clk); in execute()
207 module->addFf(NEW_ID, ff.sig_d, past_d); in execute()
H A Dfminit.cc153 module->addFf(NEW_ID, insig, outwire); in execute()
168 module->addFf(NEW_ID, outsig, ffwire); in execute()
H A Dmiter.cc342 module->addFf(NEW_ID, assume_nok, assume_q); in create_miter_assert()
/dports/cad/yosys/yosys-yosys-0.12/passes/cmds/
H A Dchformal.cc243 module->addFf(NEW_ID, orig_a, new_a); in execute()
244 module->addFf(NEW_ID, orig_en, new_en); in execute()
258 module->addFf(NEW_ID, en, w); in execute()
/dports/cad/yosys/yosys-yosys-0.12/frontends/blif/
H A Dblifparse.cc360 cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q)); in parse_blif()
/dports/cad/yosys/yosys-yosys-0.12/kernel/
H A Dff.cc555 cell = module->addFf(name, sig_d, sig_q); in emit()
H A Drtlil.h1312 …RTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &si…
H A Drtlil.cc2655 RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::S… in addFf() function in RTLIL::Module
/dports/cad/yosys/yosys-yosys-0.12/frontends/aiger/
H A Daigerparse.cc689 module->addFf(NEW_ID, d_wire, q_wire); in parse_aiger_binary()
/dports/cad/yosys/yosys-yosys-0.12/frontends/verific/
H A Dverific.cc1942 return module->addFf(name, pre_d, post_q); in addDff()
1951 return module->addFf(name, sig_d, sig_q); in addDff()
2011 return module->addFf(name, pre_d, post_q); in addAldff()