Searched refs:addLut (Results 1 – 6 of 6) sorted by relevance
| /dports/cad/yosys/yosys-yosys-0.12/passes/techmap/ |
| H A D | lut2mux.cc | 47 count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y1, lut1)); in lut2mux()
48 count += lut2mux(cell->module->addLut(NEW_ID, sig_a_lo, sig_y2, lut2)); in lut2mux()
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| H A D | abc9_ops.cc | 1265 RTLIL::Cell *cell = module->addLut(remap_name(stringf("$lut%s", mapped_cell->name.c_str())), in reintegrate()
1531 auto cell = module->addLut(NEW_ID, in reintegrate()
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| H A D | flowmap.cc | 1411 RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table); in pack_cells()
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| /dports/cad/yosys/yosys-yosys-0.12/frontends/aiger/ |
| H A D | aigerparse.cc | 456 …module->addLut(stringf("$lut$aiger%d$%d", aiger_autoidx, rootNodeID), input_sig, output_sig, std::… in parse_xaiger()
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| /dports/cad/yosys/yosys-yosys-0.12/kernel/ |
| H A D | rtlil.h | 1302 …RTLIL::Cell* addLut (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &s…
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| H A D | rtlil.cc | 2565 RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::… in addLut() function in RTLIL::Module
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