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Searched refs:add_sensitivity (Results 1 – 4 of 4) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dlogic.cc202 proc->add_sensitivity(ref->get_name()); in seq_udp_logic()
211 proc->add_sensitivity(ref->get_name()); in seq_udp_logic()
H A Dstmt.cc840 proc->add_sensitivity(ref->get_name()); in draw_synthesisable_wait()
938 wait->add_sensitivity(ref->get_name()); in draw_wait()
940 proc->add_sensitivity(ref->get_name()); in draw_wait()
973 proc->add_sensitivity(ref->get_name()); in draw_wait()
987 proc->add_sensitivity(ref->get_name()); in draw_wait()
1001 proc->add_sensitivity(ref->get_name()); in draw_wait()
H A Dvhdl_syntax.hh441 void add_sensitivity(const std::string &s) { sensitivity_.push_back(s); } in add_sensitivity() function in vhdl_wait_stmt
869 void add_sensitivity(const std::string &name);
H A Dvhdl_syntax.cc216 void vhdl_process::add_sensitivity(const std::string &name) in add_sensitivity() function in vhdl_process