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Searched refs:adll_val (Results 1 – 25 of 63) sorted by relevance

123

/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c445 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
454 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
501 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
921 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
978 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
979 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
984 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1048 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1061 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1069 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c445 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
454 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
501 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
921 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
978 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
979 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
984 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1048 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1061 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1069 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c445 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
454 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
501 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
921 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
978 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
979 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
984 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1048 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1061 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1069 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c445 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
454 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
501 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
921 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
978 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
979 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
984 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1048 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1061 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1069 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c446 adll_val++; in ddr3_tx_shift_dqs_adll_step_before_fail()
455 ECC_PUP * ecc, adll_val); in ddr3_tx_shift_dqs_adll_step_before_fail()
502 adll_val - 2, 2); in ddr3_tx_shift_dqs_adll_step_before_fail()
922 u32 adll_val = MAX_DELAY; in ddr3_rx_shift_dqs_to_first_fail() local
979 --adll_val; in ddr3_rx_shift_dqs_to_first_fail()
980 if (adll_val == ADLL_MIN) { in ddr3_rx_shift_dqs_to_first_fail()
985 0, adll_val); in ddr3_rx_shift_dqs_to_first_fail()
1049 (adll_val - 2)); in ddr3_rx_shift_dqs_to_first_fail()
1062 if (adll_val == 0) { in ddr3_rx_shift_dqs_to_first_fail()
1070 adll_val--; in ddr3_rx_shift_dqs_to_first_fail()
[all …]

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