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Searched refs:allow_signal_assignment (Results 1 – 2 of 2) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-vhdl/
H A Dstmt.cc339 !proc->get_scope()->allow_signal_assignment()) { in check_valid_assignment()
607 assert(proc->get_scope()->allow_signal_assignment()); in draw_nbassign()
619 bool emulate_blocking = proc->get_scope()->allow_signal_assignment(); in draw_assign()
H A Dvhdl_syntax.hh796 bool allow_signal_assignment() const { return sig_assign_; } in allow_signal_assignment() function in vhdl_scope