Home
last modified time | relevance | path

Searched refs:apll_parents (Results 1 – 25 of 71) sorted by relevance

123

/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/mediatek/
H A Dclk-mt8135.c334 static const char * const apll_parents[] __initconst = { variable
393 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
H A Dclk-mt2712.c570 static const char * const apll_parents[] = { variable
829 apll_parents, 0x500, 8, 4, 15),
831 apll_parents, 0x500, 16, 4, 23),
H A Dclk-mt2701.c310 static const char * const apll_parents[] = { variable
537 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/mediatek/
H A Dclk-mt8135.c334 static const char * const apll_parents[] __initconst = { variable
393 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
H A Dclk-mt2712.c570 static const char * const apll_parents[] = { variable
829 apll_parents, 0x500, 8, 4, 15),
831 apll_parents, 0x500, 16, 4, 23),
H A Dclk-mt2701.c310 static const char * const apll_parents[] = { variable
537 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/mediatek/
H A Dclk-mt8135.c334 static const char * const apll_parents[] __initconst = { variable
393 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
H A Dclk-mt2712.c570 static const char * const apll_parents[] = { variable
829 apll_parents, 0x500, 8, 4, 15),
831 apll_parents, 0x500, 16, 4, 23),
H A Dclk-mt2701.c310 static const char * const apll_parents[] = { variable
537 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c340 static const int apll_parents[] = { variable
536 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c340 static const int apll_parents[] = { variable
536 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c340 static const int apll_parents[] = { variable
536 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c340 static const int apll_parents[] = { variable
536 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/clk/mediatek/
H A Dclk-mt7623.c340 static const int apll_parents[] = { variable
536 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt7623.c343 static const int apll_parents[] = { variable
539 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt7623.c343 static const int apll_parents[] = { variable
539 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt7623.c343 static const int apll_parents[] = { variable
539 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt7623.c343 static const int apll_parents[] = { variable
539 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt7623.c343 static const int apll_parents[] = { variable
539 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt7623.c343 static const int apll_parents[] = { variable
539 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt7623.c343 static const int apll_parents[] = { variable
539 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt7623.c343 static const int apll_parents[] = { variable
539 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt7623.c343 static const int apll_parents[] = { variable
539 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt7623.c343 static const int apll_parents[] = { variable
539 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/mediatek/
H A Dclk-mt7623.c343 static const int apll_parents[] = { variable
539 MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),

123