| /dports/graphics/mesa-dri-classic/mesa-20.2.3/src/freedreno/fdl/ |
| H A D | fd6_layout.c | 87 layout->base_align = 64; in fdl6_tile_alignment()
89 layout->base_align = 128; in fdl6_tile_alignment()
91 layout->base_align = 256; in fdl6_tile_alignment()
137 layout->base_align = 64; in fdl6_layout()
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| /dports/graphics/libosmesa-gallium/mesa-21.3.6/src/freedreno/fdl/ |
| H A D | fd6_layout.c | 87 layout->base_align = 64; in fdl6_tile_alignment()
89 layout->base_align = 128; in fdl6_tile_alignment()
91 layout->base_align = 256; in fdl6_tile_alignment()
139 layout->base_align = 64; in fdl6_layout()
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| /dports/graphics/libosmesa/mesa-21.3.6/src/freedreno/fdl/ |
| H A D | fd6_layout.c | 87 layout->base_align = 64; in fdl6_tile_alignment()
89 layout->base_align = 128; in fdl6_tile_alignment()
91 layout->base_align = 256; in fdl6_tile_alignment()
139 layout->base_align = 64; in fdl6_layout()
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| /dports/graphics/mesa-libs/mesa-21.3.6/src/freedreno/fdl/ |
| H A D | fd6_layout.c | 87 layout->base_align = 64; in fdl6_tile_alignment()
89 layout->base_align = 128; in fdl6_tile_alignment()
91 layout->base_align = 256; in fdl6_tile_alignment()
139 layout->base_align = 64; in fdl6_layout()
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| /dports/graphics/mesa-gallium-va/mesa-21.3.6/src/freedreno/fdl/ |
| H A D | fd6_layout.c | 87 layout->base_align = 64; in fdl6_tile_alignment()
89 layout->base_align = 128; in fdl6_tile_alignment()
91 layout->base_align = 256; in fdl6_tile_alignment()
139 layout->base_align = 64; in fdl6_layout()
|
| /dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/freedreno/fdl/ |
| H A D | fd6_layout.c | 87 layout->base_align = 64; in fdl6_tile_alignment()
89 layout->base_align = 128; in fdl6_tile_alignment()
91 layout->base_align = 256; in fdl6_tile_alignment()
139 layout->base_align = 64; in fdl6_layout()
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| /dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/freedreno/fdl/ |
| H A D | fd6_layout.c | 87 layout->base_align = 64; in fdl6_tile_alignment()
89 layout->base_align = 128; in fdl6_tile_alignment()
91 layout->base_align = 256; in fdl6_tile_alignment()
139 layout->base_align = 64; in fdl6_layout()
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| /dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/freedreno/fdl/ |
| H A D | fd6_layout.c | 87 layout->base_align = 64; in fdl6_tile_alignment()
89 layout->base_align = 128; in fdl6_tile_alignment()
91 layout->base_align = 256; in fdl6_tile_alignment()
139 layout->base_align = 64; in fdl6_layout()
|
| /dports/graphics/mesa-dri/mesa-21.3.6/src/freedreno/fdl/ |
| H A D | fd6_layout.c | 87 layout->base_align = 64; in fdl6_tile_alignment()
89 layout->base_align = 128; in fdl6_tile_alignment()
91 layout->base_align = 256; in fdl6_tile_alignment()
139 layout->base_align = 64; in fdl6_layout()
|
| /dports/lang/clover/mesa-21.3.6/src/freedreno/fdl/ |
| H A D | fd6_layout.c | 87 layout->base_align = 64; in fdl6_tile_alignment()
89 layout->base_align = 128; in fdl6_tile_alignment()
91 layout->base_align = 256; in fdl6_tile_alignment()
139 layout->base_align = 64; in fdl6_layout()
|
| /dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/freedreno/fdl/ |
| H A D | fd6_layout.c | 91 layout->base_align = 64; in fdl6_tile_alignment()
93 layout->base_align = 128; in fdl6_tile_alignment()
95 layout->base_align = 256; in fdl6_tile_alignment()
144 layout->base_align = 64; in fdl6_layout()
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| /dports/lang/clover/mesa-21.3.6/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 258 unsigned base_align = num_pipes * pipe_interleave_bytes; in si_compute_cmask() local
279 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align)); in si_compute_cmask()
280 surf->cmask_size = align(slice_bytes, base_align) * num_layers; in si_compute_cmask()
287 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align; in si_compute_htile() local
343 base_align = num_pipes * pipe_interleave_bytes; in si_compute_htile()
345 surf->meta_alignment_log2 = util_logbase2(base_align); in si_compute_htile()
346 surf->meta_size = num_layers * align(slice_bytes, base_align); in si_compute_htile()
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| /dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 258 unsigned base_align = num_pipes * pipe_interleave_bytes; in si_compute_cmask() local
279 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align)); in si_compute_cmask()
280 surf->cmask_size = align(slice_bytes, base_align) * num_layers; in si_compute_cmask()
287 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align; in si_compute_htile() local
343 base_align = num_pipes * pipe_interleave_bytes; in si_compute_htile()
345 surf->meta_alignment_log2 = util_logbase2(base_align); in si_compute_htile()
346 surf->meta_size = num_layers * align(slice_bytes, base_align); in si_compute_htile()
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| /dports/graphics/libosmesa/mesa-21.3.6/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 258 unsigned base_align = num_pipes * pipe_interleave_bytes; in si_compute_cmask() local
279 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align)); in si_compute_cmask()
280 surf->cmask_size = align(slice_bytes, base_align) * num_layers; in si_compute_cmask()
287 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align; in si_compute_htile() local
343 base_align = num_pipes * pipe_interleave_bytes; in si_compute_htile()
345 surf->meta_alignment_log2 = util_logbase2(base_align); in si_compute_htile()
346 surf->meta_size = num_layers * align(slice_bytes, base_align); in si_compute_htile()
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| /dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 258 unsigned base_align = num_pipes * pipe_interleave_bytes; in si_compute_cmask() local
279 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align)); in si_compute_cmask()
280 surf->cmask_size = align(slice_bytes, base_align) * num_layers; in si_compute_cmask()
287 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align; in si_compute_htile() local
343 base_align = num_pipes * pipe_interleave_bytes; in si_compute_htile()
345 surf->meta_alignment_log2 = util_logbase2(base_align); in si_compute_htile()
346 surf->meta_size = num_layers * align(slice_bytes, base_align); in si_compute_htile()
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| /dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 258 unsigned base_align = num_pipes * pipe_interleave_bytes; in si_compute_cmask() local
279 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align)); in si_compute_cmask()
280 surf->cmask_size = align(slice_bytes, base_align) * num_layers; in si_compute_cmask()
287 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align; in si_compute_htile() local
343 base_align = num_pipes * pipe_interleave_bytes; in si_compute_htile()
345 surf->meta_alignment_log2 = util_logbase2(base_align); in si_compute_htile()
346 surf->meta_size = num_layers * align(slice_bytes, base_align); in si_compute_htile()
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| /dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 258 unsigned base_align = num_pipes * pipe_interleave_bytes; in si_compute_cmask() local
279 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align)); in si_compute_cmask()
280 surf->cmask_size = align(slice_bytes, base_align) * num_layers; in si_compute_cmask()
287 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align; in si_compute_htile() local
343 base_align = num_pipes * pipe_interleave_bytes; in si_compute_htile()
345 surf->meta_alignment_log2 = util_logbase2(base_align); in si_compute_htile()
346 surf->meta_size = num_layers * align(slice_bytes, base_align); in si_compute_htile()
|
| /dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 258 unsigned base_align = num_pipes * pipe_interleave_bytes; in si_compute_cmask() local
279 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align)); in si_compute_cmask()
280 surf->cmask_size = align(slice_bytes, base_align) * num_layers; in si_compute_cmask()
287 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align; in si_compute_htile() local
343 base_align = num_pipes * pipe_interleave_bytes; in si_compute_htile()
345 surf->meta_alignment_log2 = util_logbase2(base_align); in si_compute_htile()
346 surf->meta_size = num_layers * align(slice_bytes, base_align); in si_compute_htile()
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| /dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 258 unsigned base_align = num_pipes * pipe_interleave_bytes; in si_compute_cmask() local
279 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align)); in si_compute_cmask()
280 surf->cmask_size = align(slice_bytes, base_align) * num_layers; in si_compute_cmask()
287 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align; in si_compute_htile() local
343 base_align = num_pipes * pipe_interleave_bytes; in si_compute_htile()
345 surf->meta_alignment_log2 = util_logbase2(base_align); in si_compute_htile()
346 surf->meta_size = num_layers * align(slice_bytes, base_align); in si_compute_htile()
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| /dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 258 unsigned base_align = num_pipes * pipe_interleave_bytes; in si_compute_cmask() local
279 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align)); in si_compute_cmask()
280 surf->cmask_size = align(slice_bytes, base_align) * num_layers; in si_compute_cmask()
287 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align; in si_compute_htile() local
343 base_align = num_pipes * pipe_interleave_bytes; in si_compute_htile()
345 surf->meta_alignment_log2 = util_logbase2(base_align); in si_compute_htile()
346 surf->meta_size = num_layers * align(slice_bytes, base_align); in si_compute_htile()
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| /dports/graphics/mesa-dri-classic/mesa-20.2.3/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 258 unsigned base_align = num_pipes * pipe_interleave_bytes; in si_compute_cmask() local
279 surf->cmask_alignment = MAX2(256, base_align); in si_compute_cmask()
280 surf->cmask_size = align(slice_bytes, base_align) * num_layers; in si_compute_cmask()
287 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align; in si_compute_htile() local
343 base_align = num_pipes * pipe_interleave_bytes; in si_compute_htile()
345 surf->htile_alignment = base_align; in si_compute_htile()
346 surf->htile_size = num_layers * align(slice_bytes, base_align); in si_compute_htile()
|
| /dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_surface.c | 258 unsigned base_align = num_pipes * pipe_interleave_bytes; in si_compute_cmask() local
279 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align)); in si_compute_cmask()
280 surf->cmask_size = align(slice_bytes, base_align) * num_layers; in si_compute_cmask()
287 unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align; in si_compute_htile() local
343 base_align = num_pipes * pipe_interleave_bytes; in si_compute_htile()
345 surf->meta_alignment_log2 = util_logbase2(base_align); in si_compute_htile()
346 surf->meta_size = num_layers * align(slice_bytes, base_align); in si_compute_htile()
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| /dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/radeon/ |
| H A D | r600_cs.c | 254 u64 *base_align) in r600_get_array_mode_alignment() argument
269 *base_align = 1; in r600_get_array_mode_alignment()
275 *base_align = values->group_size; in r600_get_array_mode_alignment()
283 *base_align = values->group_size; in r600_get_array_mode_alignment()
291 *base_align = max(macro_tile_bytes, in r600_get_array_mode_alignment()
356 u64 base_offset, base_align; in r600_cs_track_validate_cb() local
425 base_offset, base_align, array_mode); in r600_cs_track_validate_cb()
524 u64 base_offset, base_align; in r600_cs_track_validate_db() local
615 base_offset, base_align, array_mode); in r600_cs_track_validate_db()
1447 offset = round_up(offset, base_align); in r600_texture_size()
[all …]
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| /dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/radeon/ |
| H A D | r600_cs.c | 254 u64 *base_align) in r600_get_array_mode_alignment() argument
269 *base_align = 1; in r600_get_array_mode_alignment()
275 *base_align = values->group_size; in r600_get_array_mode_alignment()
283 *base_align = values->group_size; in r600_get_array_mode_alignment()
291 *base_align = max(macro_tile_bytes, in r600_get_array_mode_alignment()
356 u64 base_offset, base_align; in r600_cs_track_validate_cb() local
425 base_offset, base_align, array_mode); in r600_cs_track_validate_cb()
524 u64 base_offset, base_align; in r600_cs_track_validate_db() local
615 base_offset, base_align, array_mode); in r600_cs_track_validate_db()
1447 offset = round_up(offset, base_align); in r600_texture_size()
[all …]
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| /dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/radeon/ |
| H A D | r600_cs.c | 254 u64 *base_align) in r600_get_array_mode_alignment() argument
269 *base_align = 1; in r600_get_array_mode_alignment()
275 *base_align = values->group_size; in r600_get_array_mode_alignment()
283 *base_align = values->group_size; in r600_get_array_mode_alignment()
291 *base_align = max(macro_tile_bytes, in r600_get_array_mode_alignment()
356 u64 base_offset, base_align; in r600_cs_track_validate_cb() local
425 base_offset, base_align, array_mode); in r600_cs_track_validate_cb()
524 u64 base_offset, base_align; in r600_cs_track_validate_db() local
615 base_offset, base_align, array_mode); in r600_cs_track_validate_db()
1447 offset = round_up(offset, base_align); in r600_texture_size()
[all …]
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