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Searched refs:bfin_write_EMAC_SYSCTL (Results 1 – 25 of 39) sorted by relevance

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/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-bf527/
H A DBF526_cdef.h50 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-bf537/
H A DBF536_cdef.h50 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-bf518/
H A DBF516_cdef.h50 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
/dports/sysutils/u-boot-utilite/u-boot-2015.07/drivers/net/
H A Dbfin_mac.c236 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/drivers/net/
H A Dbfin_mac.c264 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/drivers/net/
H A Dbfin_mac.c264 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/drivers/net/
H A Dbfin_mac.c264 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/drivers/net/
H A Dbfin_mac.c264 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/drivers/net/
H A Dbfin_mac.c264 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/drivers/net/
H A Dbfin_mac.c264 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/drivers/net/
H A Dbfin_mac.c264 bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); in bfin_miiphy_init()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/
H A DBF537_cdef.h72 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
H A DBF536_cdef.h72 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/
H A DBF536_cdef.h72 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
H A DBF537_cdef.h72 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/
H A DBF536_cdef.h72 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
H A DBF537_cdef.h72 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/
H A DBF536_cdef.h72 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
H A DBF537_cdef.h72 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/
H A DBF537_cdef.h72 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
H A DBF536_cdef.h72 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/
H A DBF537_cdef.h72 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
H A DBF536_cdef.h72 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf537/
H A DBF536_cdef.h72 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro
H A DBF537_cdef.h72 #define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) macro

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