Home
last modified time | relevance | path

Searched refs:biggest_mode (Results 1 – 25 of 224) sorted by relevance

123456789

/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/
H A Dlra-spills.c137 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
212 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
213 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
252 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
298 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
303 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
308 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
328 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
375 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/
H A Dlra-spills.c137 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
212 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
213 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
252 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
298 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
303 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
308 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
328 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
375 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/
H A Dlra-spills.c137 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
212 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
213 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
252 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
298 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
303 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
308 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
328 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
375 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/
H A Dlra-spills.c137 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
212 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
213 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
252 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
298 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
303 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
308 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
328 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
375 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/
H A Dlra-spills.c137 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
212 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
213 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
252 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
298 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
303 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
308 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
328 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
375 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/
H A Dlra-spills.c137 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
212 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
213 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
252 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
298 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
303 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
308 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
328 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
375 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()
H A Dlra-lives.c773 if (partial_subreg_p (lra_reg_info[regno].biggest_mode, in process_bb_lives()
774 reg->biggest_mode)) in process_bb_lives()
775 lra_reg_info[regno].biggest_mode = reg->biggest_mode; in process_bb_lives()
786 lra_reg_info[regno + i].biggest_mode in process_bb_lives()
877 mark_regno_live (reg->regno, reg->biggest_mode); in process_bb_lives()
887 GET_MODE_SIZE (hr->biggest_mode))) in process_bb_lives()
913 mark_regno_dead (reg->regno, reg->biggest_mode); in process_bb_lives()
994 mark_regno_live (reg->regno, reg->biggest_mode); in process_bb_lives()
1021 mark_regno_dead (reg->regno, reg->biggest_mode); in process_bb_lives()
1026 mark_regno_live (reg->regno, reg->biggest_mode); in process_bb_lives()
[all …]
/dports/lang/gcc8/gcc-8.5.0/gcc/
H A Dlra-spills.c137 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
212 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
213 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
252 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
298 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
303 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
308 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
328 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
375 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()
/dports/lang/gcc9/gcc-9.4.0/gcc/
H A Dlra-lives.c773 if (partial_subreg_p (lra_reg_info[regno].biggest_mode, in process_bb_lives()
774 reg->biggest_mode)) in process_bb_lives()
775 lra_reg_info[regno].biggest_mode = reg->biggest_mode; in process_bb_lives()
786 lra_reg_info[regno + i].biggest_mode in process_bb_lives()
877 mark_regno_live (reg->regno, reg->biggest_mode); in process_bb_lives()
887 GET_MODE_SIZE (hr->biggest_mode))) in process_bb_lives()
913 mark_regno_dead (reg->regno, reg->biggest_mode); in process_bb_lives()
994 mark_regno_live (reg->regno, reg->biggest_mode); in process_bb_lives()
1021 mark_regno_dead (reg->regno, reg->biggest_mode); in process_bb_lives()
1026 mark_regno_live (reg->regno, reg->biggest_mode); in process_bb_lives()
[all …]
H A Dlra-spills.c137 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
212 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
213 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
252 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
298 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
303 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
308 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
328 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
375 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()
H A Dlra-assigns.c486 machine_mode biggest_mode; in find_hard_regno_for_1() local
508 biggest_mode = lra_reg_info[regno].biggest_mode; in find_hard_regno_for_1()
564 lra_reg_info[conflict_regno].biggest_mode); in find_hard_regno_for_1()
580 = lra_reg_info[conflict_regno].biggest_mode; in find_hard_regno_for_1()
1154 machine_mode mode, biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms() local
1171 biggest_mode = lra_reg_info[i].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1172 biggest_nregs = hard_regno_nregs (hard_regno, biggest_mode); in setup_live_pseudos_and_spill_after_risky_transforms()
1203 mode = lra_reg_info[regno].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1232 biggest_mode = lra_reg_info[conflict_regno].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1234 biggest_mode); in setup_live_pseudos_and_spill_after_risky_transforms()
[all …]
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/
H A Dlra-lives.c773 if (partial_subreg_p (lra_reg_info[regno].biggest_mode, in process_bb_lives()
774 reg->biggest_mode)) in process_bb_lives()
775 lra_reg_info[regno].biggest_mode = reg->biggest_mode; in process_bb_lives()
786 lra_reg_info[regno + i].biggest_mode in process_bb_lives()
877 mark_regno_live (reg->regno, reg->biggest_mode); in process_bb_lives()
887 GET_MODE_SIZE (hr->biggest_mode))) in process_bb_lives()
913 mark_regno_dead (reg->regno, reg->biggest_mode); in process_bb_lives()
994 mark_regno_live (reg->regno, reg->biggest_mode); in process_bb_lives()
1021 mark_regno_dead (reg->regno, reg->biggest_mode); in process_bb_lives()
1026 mark_regno_live (reg->regno, reg->biggest_mode); in process_bb_lives()
[all …]
H A Dlra-spills.c137 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
212 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
213 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
252 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
298 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
303 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
308 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
328 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
375 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/
H A Dlra-spills.c138 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
213 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
214 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
253 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
301 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
306 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
311 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
331 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
378 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()
H A Dlra-assigns.c486 machine_mode biggest_mode; in find_hard_regno_for_1() local
505 biggest_mode = lra_reg_info[regno].biggest_mode; in find_hard_regno_for_1()
561 lra_reg_info[conflict_regno].biggest_mode); in find_hard_regno_for_1()
577 = lra_reg_info[conflict_regno].biggest_mode; in find_hard_regno_for_1()
1152 machine_mode mode, biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms() local
1169 biggest_mode = lra_reg_info[i].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1170 biggest_nregs = hard_regno_nregs (hard_regno, biggest_mode); in setup_live_pseudos_and_spill_after_risky_transforms()
1201 mode = lra_reg_info[regno].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1230 biggest_mode = lra_reg_info[conflict_regno].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1232 biggest_mode); in setup_live_pseudos_and_spill_after_risky_transforms()
[all …]
/dports/devel/avr-gcc/gcc-10.2.0/gcc/
H A Dlra-spills.c138 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
213 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
214 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
253 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
301 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
306 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
311 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
331 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
378 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()
H A Dlra-assigns.c486 machine_mode biggest_mode; in find_hard_regno_for_1() local
505 biggest_mode = lra_reg_info[regno].biggest_mode; in find_hard_regno_for_1()
561 lra_reg_info[conflict_regno].biggest_mode); in find_hard_regno_for_1()
577 = lra_reg_info[conflict_regno].biggest_mode; in find_hard_regno_for_1()
1152 machine_mode mode, biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms() local
1169 biggest_mode = lra_reg_info[i].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1170 biggest_nregs = hard_regno_nregs (hard_regno, biggest_mode); in setup_live_pseudos_and_spill_after_risky_transforms()
1201 mode = lra_reg_info[regno].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1230 biggest_mode = lra_reg_info[conflict_regno].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1232 biggest_mode); in setup_live_pseudos_and_spill_after_risky_transforms()
[all …]
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/
H A Dlra-spills.c138 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
213 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
214 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
253 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
301 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
306 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
311 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
331 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
378 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()
H A Dlra-assigns.c486 machine_mode biggest_mode; in find_hard_regno_for_1() local
505 biggest_mode = lra_reg_info[regno].biggest_mode; in find_hard_regno_for_1()
561 lra_reg_info[conflict_regno].biggest_mode); in find_hard_regno_for_1()
577 = lra_reg_info[conflict_regno].biggest_mode; in find_hard_regno_for_1()
1152 machine_mode mode, biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms() local
1169 biggest_mode = lra_reg_info[i].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1170 biggest_nregs = hard_regno_nregs (hard_regno, biggest_mode); in setup_live_pseudos_and_spill_after_risky_transforms()
1201 mode = lra_reg_info[regno].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1230 biggest_mode = lra_reg_info[conflict_regno].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1232 biggest_mode); in setup_live_pseudos_and_spill_after_risky_transforms()
[all …]
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/
H A Dlra-spills.c138 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
213 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
214 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
253 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
301 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
306 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
311 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
331 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
378 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()
H A Dlra-assigns.c486 machine_mode biggest_mode; in find_hard_regno_for_1() local
505 biggest_mode = lra_reg_info[regno].biggest_mode; in find_hard_regno_for_1()
561 lra_reg_info[conflict_regno].biggest_mode); in find_hard_regno_for_1()
577 = lra_reg_info[conflict_regno].biggest_mode; in find_hard_regno_for_1()
1152 machine_mode mode, biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms() local
1169 biggest_mode = lra_reg_info[i].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1170 biggest_nregs = hard_regno_nregs (hard_regno, biggest_mode); in setup_live_pseudos_and_spill_after_risky_transforms()
1201 mode = lra_reg_info[regno].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1230 biggest_mode = lra_reg_info[conflict_regno].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1232 biggest_mode); in setup_live_pseudos_and_spill_after_risky_transforms()
[all …]
/dports/lang/gcc11/gcc-11.2.0/gcc/
H A Dlra-spills.c138 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
213 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
214 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
253 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
301 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
306 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
311 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
331 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
378 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()
H A Dlra-assigns.c486 machine_mode biggest_mode; in find_hard_regno_for_1() local
505 biggest_mode = lra_reg_info[regno].biggest_mode; in find_hard_regno_for_1()
561 lra_reg_info[conflict_regno].biggest_mode); in find_hard_regno_for_1()
577 = lra_reg_info[conflict_regno].biggest_mode; in find_hard_regno_for_1()
1152 machine_mode mode, biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms() local
1169 biggest_mode = lra_reg_info[i].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1170 biggest_nregs = hard_regno_nregs (hard_regno, biggest_mode); in setup_live_pseudos_and_spill_after_risky_transforms()
1201 mode = lra_reg_info[regno].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1230 biggest_mode = lra_reg_info[conflict_regno].biggest_mode; in setup_live_pseudos_and_spill_after_risky_transforms()
1232 biggest_mode); in setup_live_pseudos_and_spill_after_risky_transforms()
[all …]
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/
H A Dlra-spills.c138 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
213 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
214 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
253 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
301 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
306 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
311 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
331 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
378 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()
/dports/lang/gcc10/gcc-10.3.0/gcc/
H A Dlra-spills.c138 = wider_subreg_mode (mode, lra_reg_info[i].biggest_mode); in assign_mem_slot()
213 poly_int64 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode); in pseudo_reg_slot_compare()
214 poly_int64 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode); in pseudo_reg_slot_compare()
253 lra_reg_info[i].biggest_mode, hard_regno); in assign_spill_hard_regs()
282 mode = lra_reg_info[regno].biggest_mode; in assign_spill_hard_regs()
301 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
306 lra_reg_info[regno].biggest_mode, hard_regno); in assign_spill_hard_regs()
311 lra_reg_info[regno].biggest_mode); in assign_spill_hard_regs()
331 lra_reg_info[regno].biggest_mode); in add_pseudo_to_slot()
378 lra_reg_info[regno].biggest_mode); in assign_stack_slot_num_and_sort_pseudos()

123456789