/dports/games/libretro-fbneo/FBNeo-bbe3c05/src/burn/ |
H A D | bitswap.h | 3 bit23, bit22, bit21, bit20, bit19, bit18, bit17, bit16, \ argument 18 ((((n) >> (bit19)) & 1) << 19) | \ 40 bit23, bit22, bit21, bit20, bit19, bit18, bit17, bit16, \ argument 47 ((((n) >> (bit19)) & 1) << 19) | \
|
/dports/games/libretro-fbalpha/fbalpha-84eb9d9/src/burn/ |
H A D | bitswap.h | 3 bit23, bit22, bit21, bit20, bit19, bit18, bit17, bit16, \ argument 18 ((((n) >> (bit19)) & 1) << 19) | \ 40 bit23, bit22, bit21, bit20, bit19, bit18, bit17, bit16, \ argument 47 ((((n) >> (bit19)) & 1) << 19) | \
|
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/board/buffalo/lsxl/ |
H A D | kwbimage-lschl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
|
H A D | kwbimage-lsxhl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
|
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/board/buffalo/lsxl/ |
H A D | kwbimage-lschl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
|
H A D | kwbimage-lsxhl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
|
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/buffalo/lsxl/ |
H A D | kwbimage-lsxhl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
|
H A D | kwbimage-lschl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
|
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/buffalo/lsxl/ |
H A D | kwbimage-lschl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
|
H A D | kwbimage-lsxhl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
|
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/board/buffalo/lsxl/ |
H A D | kwbimage-lschl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
|
H A D | kwbimage-lsxhl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
|
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/board/buffalo/lsxl/ |
H A D | kwbimage-lschl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
|
H A D | kwbimage-lsxhl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
|
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/board/buffalo/lsxl/ |
H A D | kwbimage-lschl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
|
H A D | kwbimage-lsxhl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
|
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/board/buffalo/lsxl/ |
H A D | kwbimage-lsxhl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
|
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/board/buffalo/lsxl/ |
H A D | kwbimage-lschl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
|
H A D | kwbimage-lsxhl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
|
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/board/buffalo/lsxl/ |
H A D | kwbimage-lschl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
|
H A D | kwbimage-lsxhl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
|
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/board/buffalo/lsxl/ |
H A D | kwbimage-lschl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
|
/dports/sysutils/u-boot-sopine/u-boot-2021.07/board/buffalo/lsxl/ |
H A D | kwbimage-lschl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b1100, (write) M_ODT[0] is asserted during write to DRAM CS2, CS3
|
H A D | kwbimage-lsxhl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
|
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/board/buffalo/lsxl/ |
H A D | kwbimage-lsxhl.cfg | 47 # bit19: 0 required 59 # bit19-16: 2, 3 cyle tWTR 86 # bit19: 0, Cs3AddrSel 142 # bit19-16: 8, 8 cycles from read command to de-assertion of internal ODT signal 150 # bit19-16: 8, 8 cycles from write command to de-assertion of internal ODT signal 182 # bit19-16: 0b0001, (write) M_ODT[0] is asserted during write to DRAM CS0
|