| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 332 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
338 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
341 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
474 static inline int look_for(u32 bytelane) in look_for() argument
505 if (!incr_dly(bytelane)) in look_for()
514 static inline int look_past(u32 bytelane) in look_past() argument
547 if (!incr_dly(bytelane)) in look_past()
558 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
572 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
671 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 332 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
338 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
341 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
474 static inline int look_for(u32 bytelane) in look_for() argument
505 if (!incr_dly(bytelane)) in look_for()
514 static inline int look_past(u32 bytelane) in look_past() argument
547 if (!incr_dly(bytelane)) in look_past()
558 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
572 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
671 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 332 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
338 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
341 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
474 static inline int look_for(u32 bytelane) in look_for() argument
505 if (!incr_dly(bytelane)) in look_for()
514 static inline int look_past(u32 bytelane) in look_past() argument
547 if (!incr_dly(bytelane)) in look_past()
558 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
572 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
671 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 332 static inline void set_dly(u32 bytelane, u32 dly)
338 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane));
341 static inline bool incr_dly(u32 bytelane)
474 static inline int look_for(u32 bytelane)
505 if (!incr_dly(bytelane))
514 static inline int look_past(u32 bytelane)
547 if (!incr_dly(bytelane))
558 set_dly(bytelane, 0); /* Start training at DQS=0 */
572 center_dly(bytelane, dqs_s);
671 set_dly(bytelane, 0); /* Start training at DQS=0 */
[all …]
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 332 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
338 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
341 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
474 static inline int look_for(u32 bytelane) in look_for() argument
505 if (!incr_dly(bytelane)) in look_for()
514 static inline int look_past(u32 bytelane) in look_past() argument
547 if (!incr_dly(bytelane)) in look_past()
558 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
572 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
671 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/mips/mach-mscc/include/mach/ |
| H A D | ddr.h | 335 static inline void set_dly(u32 bytelane, u32 dly) in set_dly() argument
341 writel(r, BASE_CFG + ICPU_MEMCTRL_DQS_DLY(bytelane)); in set_dly()
344 static inline bool incr_dly(u32 bytelane) in incr_dly() argument
500 static inline int look_for(u32 bytelane) in look_for() argument
531 if (!incr_dly(bytelane)) in look_for()
540 static inline int look_past(u32 bytelane) in look_past() argument
573 if (!incr_dly(bytelane)) in look_past()
584 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
598 center_dly(bytelane, dqs_s); in hal_vcoreiii_train_bytelane()
697 set_dly(bytelane, 0); /* Start training at DQS=0 */ in hal_vcoreiii_train_bytelane()
[all …]
|