1 /*
2 * nextpnr -- Next Generation Place and Route
3 *
4 * Copyright (C) 2018 David Shah <david@symbioticeda.com>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include <algorithm>
21 #include <boost/optional.hpp>
22 #include <iterator>
23 #include <queue>
24 #include <unordered_set>
25 #include "cells.h"
26 #include "chain_utils.h"
27 #include "design_utils.h"
28 #include "globals.h"
29 #include "log.h"
30 #include "timing.h"
31 #include "util.h"
32 NEXTPNR_NAMESPACE_BEGIN
33
is_nextpnr_iob(Context * ctx,CellInfo * cell)34 static bool is_nextpnr_iob(Context *ctx, CellInfo *cell)
35 {
36 return cell->type == ctx->id("$nextpnr_ibuf") || cell->type == ctx->id("$nextpnr_obuf") ||
37 cell->type == ctx->id("$nextpnr_iobuf");
38 }
39
40 class Ecp5Packer
41 {
42 public:
Ecp5Packer(Context * ctx)43 Ecp5Packer(Context *ctx) : ctx(ctx){};
44
45 private:
46 // Process the contents of packed_cells and new_cells
flush_cells()47 void flush_cells()
48 {
49 for (auto pcell : packed_cells) {
50 ctx->cells.erase(pcell);
51 }
52 for (auto &ncell : new_cells) {
53 ctx->cells[ncell->name] = std::move(ncell);
54 }
55 packed_cells.clear();
56 new_cells.clear();
57 }
58
59 // Print logic usgage
60 int available_slices = 0;
print_logic_usage()61 void print_logic_usage()
62 {
63 int total_luts = 0, total_ffs = 0;
64 int total_ramluts = 0, total_ramwluts = 0;
65 for (auto bel : ctx->getBels()) {
66 if (ctx->getBelType(bel) == id_TRELLIS_SLICE) {
67 available_slices += 1;
68 total_luts += 2;
69 total_ffs += 2;
70 Loc l = ctx->getBelLocation(bel);
71 if (l.z == 0 || l.z == 1)
72 total_ramluts += 2;
73 if (l.z == 2)
74 total_ramwluts += 2;
75 }
76 }
77 int used_lgluts = 0, used_cyluts = 0, used_ramluts = 0, used_ramwluts = 0, used_ffs = 0;
78 for (auto &cell : ctx->cells) {
79 CellInfo *ci = cell.second.get();
80 if (is_lut(ctx, ci))
81 ++used_lgluts;
82 if (is_carry(ctx, ci))
83 used_cyluts += 2;
84 if (is_dpram(ctx, ci)) {
85 used_ramluts += 4;
86 used_ramwluts += 2;
87 }
88 if (is_ff(ctx, ci))
89 used_ffs += 2;
90 }
91 log_info("Logic utilisation before packing:\n");
92 auto pc = [](int used, int total) { return 100 * used / total; };
93 int used_luts = used_lgluts + used_cyluts + used_ramluts + used_ramwluts;
94 log_info(" Total LUT4s: %5d/%5d %5d%%\n", used_luts, total_luts, pc(used_luts, total_luts));
95 log_info(" logic LUTs: %5d/%5d %5d%%\n", used_lgluts, total_luts, pc(used_lgluts, total_luts));
96 log_info(" carry LUTs: %5d/%5d %5d%%\n", used_cyluts, total_luts, pc(used_cyluts, total_luts));
97 log_info(" RAM LUTs: %5d/%5d %5d%%\n", used_ramluts, total_ramluts, pc(used_ramluts, total_ramluts));
98 log_info(" RAMW LUTs: %5d/%5d %5d%%\n", used_ramwluts, total_ramwluts,
99 pc(used_ramwluts, total_ramwluts));
100 log_break();
101 log_info(" Total DFFs: %5d/%5d %5d%%\n", used_ffs, total_ffs, pc(used_ffs, total_ffs));
102 log_break();
103 }
104
105 // Find FFs associated with LUTs, or LUT expansion muxes
find_lutff_pairs()106 void find_lutff_pairs()
107 {
108 log_info("Finding LUTFF pairs...\n");
109 for (auto cell : sorted(ctx->cells)) {
110 CellInfo *ci = cell.second;
111 if (is_lut(ctx, ci) || is_pfumx(ctx, ci) || is_l6mux(ctx, ci)) {
112 NetInfo *znet = ci->ports.at(ctx->id("Z")).net;
113 if (znet != nullptr) {
114 CellInfo *ff = net_only_drives(ctx, znet, is_ff, ctx->id("DI"), false);
115 // Can't combine preload FF with LUT due to conflict on M
116 if (ff != nullptr && get_net_or_empty(ff, ctx->id("M")) == nullptr) {
117 lutffPairs[ci->name] = ff->name;
118 fflutPairs[ff->name] = ci->name;
119 }
120 }
121 }
122 }
123 }
124
125 // Check if a flipflop is available in a slice
is_ff_available(CellInfo * slice,int ff)126 bool is_ff_available(CellInfo *slice, int ff)
127 {
128 if (get_net_or_empty(slice, (ff == 1) ? id_Q1 : id_Q0) != nullptr)
129 return false;
130 if (get_net_or_empty(slice, (ff == 1) ? id_M1 : id_M0) != nullptr)
131 return false;
132 return true;
133 }
134
135 // Check if a flipflop can be added to a slice
can_add_ff_to_slice(CellInfo * slice,CellInfo * ff)136 bool can_add_ff_to_slice(CellInfo *slice, CellInfo *ff)
137 {
138 std::string clkmux = str_or_default(ff->params, ctx->id("CLKMUX"), "CLK");
139 std::string lsrmux = str_or_default(ff->params, ctx->id("LSRMUX"), "LSR");
140
141 bool has_dpram = str_or_default(slice->params, ctx->id("MODE"), "LOGIC") == "DPRAM";
142 if (has_dpram) {
143 std::string wckmux = str_or_default(slice->params, ctx->id("WCKMUX"), "WCK");
144 std::string wremux = str_or_default(slice->params, ctx->id("WREMUX"), "WRE");
145 if (wckmux != clkmux && !(wckmux == "WCK" && clkmux == "CLK"))
146 return false;
147 if (wremux != lsrmux && !(wremux == "WRE" && lsrmux == "LSR"))
148 return false;
149 }
150 bool has_ff0 = get_net_or_empty(slice, id_Q0) != nullptr;
151 bool has_ff1 = get_net_or_empty(slice, id_Q1) != nullptr;
152 if (!has_ff0 && !has_ff1)
153 return true;
154 if (str_or_default(ff->params, ctx->id("GSR"), "DISABLED") !=
155 str_or_default(slice->params, ctx->id("GSR"), "DISABLED"))
156 return false;
157 if (str_or_default(ff->params, ctx->id("SRMODE"), "LSR_OVER_CE") !=
158 str_or_default(slice->params, ctx->id("SRMODE"), "LSR_OVER_CE"))
159 return false;
160 if (str_or_default(ff->params, ctx->id("CEMUX"), "1") != str_or_default(slice->params, ctx->id("CEMUX"), "1"))
161 return false;
162 if (str_or_default(ff->params, ctx->id("LSRMUX"), "LSR") !=
163 str_or_default(slice->params, ctx->id("LSRMUX"), "LSR"))
164 return false;
165 if (str_or_default(ff->params, ctx->id("CLKMUX"), "CLK") !=
166 str_or_default(slice->params, ctx->id("CLKMUX"), "CLK"))
167 return false;
168 if (net_or_nullptr(ff, ctx->id("CLK")) != net_or_nullptr(slice, ctx->id("CLK")))
169 return false;
170 if (net_or_nullptr(ff, ctx->id("CE")) != net_or_nullptr(slice, ctx->id("CE")))
171 return false;
172 if (net_or_nullptr(ff, ctx->id("LSR")) != net_or_nullptr(slice, ctx->id("LSR")))
173 return false;
174 return true;
175 }
176
net_or_nullptr(CellInfo * cell,IdString port)177 const NetInfo *net_or_nullptr(CellInfo *cell, IdString port)
178 {
179 auto fnd = cell->ports.find(port);
180 if (fnd == cell->ports.end())
181 return nullptr;
182 else
183 return fnd->second.net;
184 }
185
186 // Return whether two FFs can be packed together in the same slice
can_pack_ffs(CellInfo * ff0,CellInfo * ff1)187 bool can_pack_ffs(CellInfo *ff0, CellInfo *ff1)
188 {
189 if (str_or_default(ff0->params, ctx->id("GSR"), "DISABLED") !=
190 str_or_default(ff1->params, ctx->id("GSR"), "DISABLED"))
191 return false;
192 if (str_or_default(ff0->params, ctx->id("SRMODE"), "LSR_OVER_CE") !=
193 str_or_default(ff1->params, ctx->id("SRMODE"), "LSR_OVER_CE"))
194 return false;
195 if (str_or_default(ff0->params, ctx->id("CEMUX"), "1") != str_or_default(ff1->params, ctx->id("CEMUX"), "1"))
196 return false;
197 if (str_or_default(ff0->params, ctx->id("LSRMUX"), "LSR") !=
198 str_or_default(ff1->params, ctx->id("LSRMUX"), "LSR"))
199 return false;
200 if (str_or_default(ff0->params, ctx->id("CLKMUX"), "CLK") !=
201 str_or_default(ff1->params, ctx->id("CLKMUX"), "CLK"))
202 return false;
203 if (net_or_nullptr(ff0, ctx->id("CLK")) != net_or_nullptr(ff1, ctx->id("CLK")))
204 return false;
205 if (net_or_nullptr(ff0, ctx->id("CE")) != net_or_nullptr(ff1, ctx->id("CE")))
206 return false;
207 if (net_or_nullptr(ff0, ctx->id("LSR")) != net_or_nullptr(ff1, ctx->id("LSR")))
208 return false;
209 return true;
210 }
211
212 // Return whether or not an FF can be added to a tile (pairing checks must also be done using the fn above)
can_add_ff_to_tile(const std::vector<CellInfo * > & tile_ffs,CellInfo * ff0)213 bool can_add_ff_to_tile(const std::vector<CellInfo *> &tile_ffs, CellInfo *ff0)
214 {
215 for (const auto &existing : tile_ffs) {
216 if (net_or_nullptr(existing, ctx->id("CLK")) != net_or_nullptr(ff0, ctx->id("CLK")))
217 return false;
218 if (net_or_nullptr(existing, ctx->id("LSR")) != net_or_nullptr(ff0, ctx->id("LSR")))
219 return false;
220 if (str_or_default(existing->params, ctx->id("CLKMUX"), "CLK") !=
221 str_or_default(ff0->params, ctx->id("CLKMUX"), "CLK"))
222 return false;
223 if (str_or_default(existing->params, ctx->id("LSRMUX"), "LSR") !=
224 str_or_default(ff0->params, ctx->id("LSRMUX"), "LSR"))
225 return false;
226 if (str_or_default(existing->params, ctx->id("SRMODE"), "LSR_OVER_CE") !=
227 str_or_default(ff0->params, ctx->id("SRMODE"), "LSR_OVER_CE"))
228 return false;
229 }
230 return true;
231 }
232
233 // Return true if a FF can be added to a DPRAM slice
can_pack_ff_dram(CellInfo * dpram,CellInfo * ff)234 bool can_pack_ff_dram(CellInfo *dpram, CellInfo *ff)
235 {
236 if (get_net_or_empty(ff, ctx->id("M")) != nullptr)
237 return false; // skip PRLD FFs due to M/DI conflict
238 std::string wckmux = str_or_default(dpram->params, ctx->id("WCKMUX"), "WCK");
239 std::string clkmux = str_or_default(ff->params, ctx->id("CLKMUX"), "CLK");
240 if (wckmux != clkmux && !(wckmux == "WCK" && clkmux == "CLK"))
241 return false;
242 std::string wremux = str_or_default(dpram->params, ctx->id("WREMUX"), "WRE");
243 std::string lsrmux = str_or_default(ff->params, ctx->id("LSRMUX"), "LSR");
244 if (wremux != lsrmux && !(wremux == "WRE" && lsrmux == "LSR"))
245 return false;
246 return true;
247 }
248
249 // Return true if two LUTs can be paired considering FF compatibility
can_pack_lutff(IdString lut0,IdString lut1)250 bool can_pack_lutff(IdString lut0, IdString lut1)
251 {
252 auto ff0 = lutffPairs.find(lut0), ff1 = lutffPairs.find(lut1);
253 if (ff0 != lutffPairs.end() && ff1 != lutffPairs.end()) {
254 return can_pack_ffs(ctx->cells.at(ff0->second).get(), ctx->cells.at(ff1->second).get());
255 } else {
256 return true;
257 }
258 }
259
260 // Find "closely connected" LUTs and pair them together
pair_luts()261 void pair_luts()
262 {
263 log_info("Finding LUT-LUT pairs...\n");
264 std::unordered_set<IdString> procdLuts;
265 for (auto cell : sorted(ctx->cells)) {
266 CellInfo *ci = cell.second;
267 if (is_lut(ctx, ci) && procdLuts.find(cell.first) == procdLuts.end()) {
268 NetInfo *znet = ci->ports.at(ctx->id("Z")).net;
269 std::vector<NetInfo *> inpnets;
270 if (znet != nullptr) {
271 for (auto user : znet->users) {
272 if (is_lut(ctx, user.cell) && user.cell != ci &&
273 procdLuts.find(user.cell->name) == procdLuts.end()) {
274 if (can_pack_lutff(ci->name, user.cell->name)) {
275 procdLuts.insert(ci->name);
276 procdLuts.insert(user.cell->name);
277 lutPairs[ci->name] = user.cell->name;
278 goto paired;
279 }
280 }
281 }
282 if (false) {
283 paired:
284 continue;
285 }
286 }
287 if (lutffPairs.find(ci->name) != lutffPairs.end()) {
288 NetInfo *qnet = ctx->cells.at(lutffPairs[ci->name])->ports.at(ctx->id("Q")).net;
289 if (qnet != nullptr) {
290 for (auto user : qnet->users) {
291 if (is_lut(ctx, user.cell) && user.cell != ci &&
292 procdLuts.find(user.cell->name) == procdLuts.end()) {
293 if (can_pack_lutff(ci->name, user.cell->name)) {
294 procdLuts.insert(ci->name);
295 procdLuts.insert(user.cell->name);
296 lutPairs[ci->name] = user.cell->name;
297 goto paired_ff;
298 }
299 }
300 }
301 if (false) {
302 paired_ff:
303 continue;
304 }
305 }
306 }
307 for (const char *inp : {"A", "B", "C", "D"}) {
308 if (!ci->ports.count(ctx->id(inp)))
309 continue;
310 NetInfo *innet = ci->ports.at(ctx->id(inp)).net;
311 if (innet != nullptr && innet->driver.cell != nullptr) {
312 CellInfo *drv = innet->driver.cell;
313 if (is_lut(ctx, drv) && drv != ci && innet->driver.port == ctx->id("Z")) {
314 if (procdLuts.find(drv->name) == procdLuts.end()) {
315 if (can_pack_lutff(ci->name, drv->name)) {
316 procdLuts.insert(ci->name);
317 procdLuts.insert(drv->name);
318 lutPairs[ci->name] = drv->name;
319 goto paired_inlut;
320 }
321 }
322 } else if (is_ff(ctx, drv) && innet->driver.port == ctx->id("Q")) {
323 auto fflut = fflutPairs.find(drv->name);
324 if (fflut != fflutPairs.end() && fflut->second != ci->name &&
325 procdLuts.find(fflut->second) == procdLuts.end()) {
326 if (can_pack_lutff(ci->name, fflut->second)) {
327 procdLuts.insert(ci->name);
328 procdLuts.insert(fflut->second);
329 lutPairs[ci->name] = fflut->second;
330 goto paired_inlut;
331 }
332 }
333 }
334 }
335 }
336
337 // Pack LUTs feeding the same CCU2, RAM or DFF into a SLICE
338 if (znet != nullptr && znet->users.size() < 10) {
339 for (auto user : znet->users) {
340 if (is_lc(ctx, user.cell) || user.cell->type == ctx->id("DP16KD") || is_ff(ctx, user.cell)) {
341 for (auto port : user.cell->ports) {
342 if (port.second.type != PORT_IN || port.second.net == nullptr ||
343 port.second.net == znet)
344 continue;
345 if (port.second.net->users.size() > 10)
346 continue;
347 CellInfo *drv = port.second.net->driver.cell;
348 if (drv == nullptr)
349 continue;
350 if (is_lut(ctx, drv) && !procdLuts.count(drv->name) &&
351 can_pack_lutff(ci->name, drv->name)) {
352 procdLuts.insert(ci->name);
353 procdLuts.insert(drv->name);
354 lutPairs[ci->name] = drv->name;
355 goto paired_inlut;
356 }
357 }
358 }
359 }
360 }
361
362 // Pack LUTs sharing an input with a simple fanout-based heuristic
363 for (const char *inp : {"A", "B", "C", "D"}) {
364 if (!ci->ports.count(ctx->id(inp)))
365 continue;
366 NetInfo *innet = ci->ports.at(ctx->id(inp)).net;
367 if (innet != nullptr && innet->users.size() < 5 && innet->users.size() > 1)
368 inpnets.push_back(innet);
369 }
370 std::sort(inpnets.begin(), inpnets.end(),
371 [&](const NetInfo *a, const NetInfo *b) { return a->users.size() < b->users.size(); });
372 for (auto inet : inpnets) {
373 for (auto &user : inet->users) {
374 if (user.cell == nullptr || user.cell == ci || !is_lut(ctx, user.cell))
375 continue;
376 if (procdLuts.count(user.cell->name))
377 continue;
378 if (can_pack_lutff(ci->name, user.cell->name)) {
379 procdLuts.insert(ci->name);
380 procdLuts.insert(user.cell->name);
381 lutPairs[ci->name] = user.cell->name;
382 goto paired_inlut;
383 }
384 }
385 }
386
387 if (false) {
388 paired_inlut:
389 continue;
390 }
391 }
392 }
393 if (ctx->debug) {
394 log_info("Singleton LUTs (packer QoR debug): \n");
395 for (auto cell : sorted(ctx->cells))
396 if (is_lut(ctx, cell.second) && !procdLuts.count(cell.first))
397 log_info(" %s\n", cell.first.c_str(ctx));
398 }
399 }
400
401 // Return true if an port is a top level port that provides its own IOBUF
is_top_port(PortRef & port)402 bool is_top_port(PortRef &port)
403 {
404 if (port.cell == nullptr)
405 return false;
406 if (port.cell->type == id_DCUA) {
407 return port.port == id_CH0_HDINP || port.port == id_CH0_HDINN || port.port == id_CH0_HDOUTP ||
408 port.port == id_CH0_HDOUTN || port.port == id_CH1_HDINP || port.port == id_CH1_HDINN ||
409 port.port == id_CH1_HDOUTP || port.port == id_CH1_HDOUTN;
410 } else if (port.cell->type == id_EXTREFB) {
411 return port.port == id_REFCLKP || port.port == id_REFCLKN;
412 } else {
413 return false;
414 }
415 }
416
417 // Return true if a net only drives a top port
drives_top_port(NetInfo * net,PortRef & tp)418 bool drives_top_port(NetInfo *net, PortRef &tp)
419 {
420 if (net == nullptr)
421 return false;
422 for (auto user : net->users) {
423 if (is_top_port(user)) {
424 if (net->users.size() > 1)
425 log_error(" port %s.%s must be connected to (and only to) a top level pin\n",
426 user.cell->name.c_str(ctx), user.port.c_str(ctx));
427 tp = user;
428 return true;
429 }
430 }
431 if (net->driver.cell != nullptr && is_top_port(net->driver)) {
432 if (net->users.size() > 1)
433 log_error(" port %s.%s must be connected to (and only to) a top level pin\n",
434 net->driver.cell->name.c_str(ctx), net->driver.port.c_str(ctx));
435 tp = net->driver;
436 return true;
437 }
438 return false;
439 }
440
441 // Simple "packer" to remove nextpnr IOBUFs, this assumes IOBUFs are manually instantiated
pack_io()442 void pack_io()
443 {
444 log_info("Packing IOs..\n");
445
446 for (auto cell : sorted(ctx->cells)) {
447 CellInfo *ci = cell.second;
448 if (is_nextpnr_iob(ctx, ci)) {
449 CellInfo *trio = nullptr;
450 NetInfo *ionet = nullptr;
451 PortRef tp;
452 if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
453 ionet = ci->ports.at(ctx->id("O")).net;
454 trio = net_only_drives(ctx, ionet, is_trellis_io, ctx->id("B"), true, ci);
455
456 } else if (ci->type == ctx->id("$nextpnr_obuf")) {
457 ionet = ci->ports.at(ctx->id("I")).net;
458 trio = net_only_drives(ctx, ci->ports.at(ctx->id("I")).net, is_trellis_io, ctx->id("B"), true, ci);
459 }
460 if (bool_or_default(ctx->settings, ctx->id("arch.ooc"))) {
461 // No IO buffer insertion in out-of-context mode, just remove the nextpnr buffer
462 // and leave the top level port
463 for (auto &port : ci->ports)
464 disconnect_port(ctx, ci, port.first);
465 } else if (trio != nullptr) {
466 // Trivial case, TRELLIS_IO used. Just remove the IOBUF
467 log_info("%s feeds TRELLIS_IO %s, removing %s %s.\n", ci->name.c_str(ctx), trio->name.c_str(ctx),
468 ci->type.c_str(ctx), ci->name.c_str(ctx));
469
470 NetInfo *net = trio->ports.at(ctx->id("B")).net;
471 if (((ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) &&
472 net->users.size() > 1) ||
473 (ci->type == ctx->id("$nextpnr_obuf") &&
474 (net->users.size() > 2 || net->driver.cell != nullptr)) ||
475 (ci->type == ctx->id("$nextpnr_iobuf") && ci->ports.at(ctx->id("I")).net != nullptr &&
476 ci->ports.at(ctx->id("I")).net->driver.cell != nullptr))
477 log_error("Pin B of %s '%s' connected to more than a single top level IO.\n",
478 trio->type.c_str(ctx), trio->name.c_str(ctx));
479 if (net != nullptr) {
480 if (net->clkconstr != nullptr && trio->ports.count(ctx->id("O"))) {
481 NetInfo *onet = trio->ports.at(ctx->id("O")).net;
482 if (onet != nullptr && !onet->clkconstr) {
483 // Move clock constraint from IO pad to input buffer output
484 std::swap(net->clkconstr, onet->clkconstr);
485 }
486 }
487 }
488 } else if (drives_top_port(ionet, tp)) {
489 log_info("%s feeds %s %s.%s, removing %s %s.\n", ci->name.c_str(ctx), tp.cell->type.c_str(ctx),
490 tp.cell->name.c_str(ctx), tp.port.c_str(ctx), ci->type.c_str(ctx), ci->name.c_str(ctx));
491 if (ionet != nullptr) {
492 ctx->nets.erase(ionet->name);
493 tp.cell->ports.at(tp.port).net = nullptr;
494 }
495 if (ci->type == ctx->id("$nextpnr_iobuf")) {
496 NetInfo *net2 = ci->ports.at(ctx->id("I")).net;
497 if (net2 != nullptr) {
498 ctx->nets.erase(net2->name);
499 }
500 }
501 } else {
502 // Create a TRELLIS_IO buffer
503 std::unique_ptr<CellInfo> tr_cell =
504 create_ecp5_cell(ctx, ctx->id("TRELLIS_IO"), ci->name.str(ctx) + "$tr_io");
505 nxio_to_tr(ctx, ci, tr_cell.get(), new_cells, packed_cells);
506 new_cells.push_back(std::move(tr_cell));
507 trio = new_cells.back().get();
508 }
509 for (auto port : ci->ports)
510 disconnect_port(ctx, ci, port.first);
511 packed_cells.insert(ci->name);
512 if (trio != nullptr) {
513 for (const auto &attr : ci->attrs)
514 trio->attrs[attr.first] = attr.second;
515
516 auto loc_attr = trio->attrs.find(ctx->id("LOC"));
517 if (loc_attr != trio->attrs.end()) {
518 std::string pin = loc_attr->second.as_string();
519 BelId pinBel = ctx->getPackagePinBel(pin);
520 if (pinBel == BelId()) {
521 log_error("IO pin '%s' constrained to pin '%s', which does not exist for package '%s'.\n",
522 trio->name.c_str(ctx), pin.c_str(), ctx->args.package.c_str());
523 } else {
524 log_info("pin '%s' constrained to Bel '%s'.\n", trio->name.c_str(ctx),
525 ctx->getBelName(pinBel).c_str(ctx));
526 }
527 trio->attrs[ctx->id("BEL")] = ctx->getBelName(pinBel).str(ctx);
528 }
529 }
530 }
531 }
532 flush_cells();
533 }
534
535 // Pass to pack LUT5s into a newly created slice
pack_lut5xs()536 void pack_lut5xs()
537 {
538 log_info("Packing LUT5-7s...\n");
539 for (auto cell : sorted(ctx->cells)) {
540 CellInfo *ci = cell.second;
541 if (is_pfumx(ctx, ci)) {
542 std::unique_ptr<CellInfo> packed =
543 create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
544 NetInfo *f0 = ci->ports.at(ctx->id("BLUT")).net;
545 if (f0 == nullptr)
546 log_error("PFUMX '%s' has disconnected port 'BLUT'\n", ci->name.c_str(ctx));
547 NetInfo *f1 = ci->ports.at(ctx->id("ALUT")).net;
548 if (f1 == nullptr)
549 log_error("PFUMX '%s' has disconnected port 'ALUT'\n", ci->name.c_str(ctx));
550 CellInfo *lut0 = net_driven_by(ctx, f0, is_lut, ctx->id("Z"));
551 CellInfo *lut1 = net_driven_by(ctx, f1, is_lut, ctx->id("Z"));
552 if (lut0 == nullptr)
553 log_error("PFUMX '%s' has BLUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
554 if (lut1 == nullptr)
555 log_error("PFUMX '%s' has ALUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
556 if (ctx->verbose)
557 log_info(" mux '%s' forms part of a LUT5\n", cell.first.c_str(ctx));
558 replace_port(lut0, ctx->id("A"), packed.get(), ctx->id("A0"));
559 replace_port(lut0, ctx->id("B"), packed.get(), ctx->id("B0"));
560 replace_port(lut0, ctx->id("C"), packed.get(), ctx->id("C0"));
561 replace_port(lut0, ctx->id("D"), packed.get(), ctx->id("D0"));
562 replace_port(lut1, ctx->id("A"), packed.get(), ctx->id("A1"));
563 replace_port(lut1, ctx->id("B"), packed.get(), ctx->id("B1"));
564 replace_port(lut1, ctx->id("C"), packed.get(), ctx->id("C1"));
565 replace_port(lut1, ctx->id("D"), packed.get(), ctx->id("D1"));
566 replace_port(ci, ctx->id("C0"), packed.get(), ctx->id("M0"));
567 replace_port(ci, ctx->id("Z"), packed.get(), ctx->id("OFX0"));
568 packed->params[ctx->id("LUT0_INITVAL")] =
569 get_or_default(lut0->params, ctx->id("INIT"), Property(0, 16));
570 packed->params[ctx->id("LUT1_INITVAL")] =
571 get_or_default(lut1->params, ctx->id("INIT"), Property(0, 16));
572
573 ctx->nets.erase(f0->name);
574 ctx->nets.erase(f1->name);
575 sliceUsage[packed->name].lut0_used = true;
576 sliceUsage[packed->name].lut1_used = true;
577 sliceUsage[packed->name].mux5_used = true;
578
579 if (lutffPairs.find(ci->name) != lutffPairs.end()) {
580 CellInfo *ff = ctx->cells.at(lutffPairs[ci->name]).get();
581 ff_to_slice(ctx, ff, packed.get(), 0, true);
582 packed_cells.insert(ff->name);
583 sliceUsage[packed->name].ff0_used = true;
584 lutffPairs.erase(ci->name);
585 fflutPairs.erase(ff->name);
586 }
587
588 new_cells.push_back(std::move(packed));
589 packed_cells.insert(lut0->name);
590 packed_cells.insert(lut1->name);
591 packed_cells.insert(ci->name);
592 }
593 }
594 flush_cells();
595 // Pack LUT6s
596 for (auto cell : sorted(ctx->cells)) {
597 CellInfo *ci = cell.second;
598 if (is_l6mux(ctx, ci)) {
599 NetInfo *ofx0_0 = ci->ports.at(ctx->id("D0")).net;
600 if (ofx0_0 == nullptr)
601 log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
602 NetInfo *ofx0_1 = ci->ports.at(ctx->id("D1")).net;
603 if (ofx0_1 == nullptr)
604 log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
605 CellInfo *slice0 = net_driven_by(ctx, ofx0_0, is_lc, ctx->id("OFX0"));
606 CellInfo *slice1 = net_driven_by(ctx, ofx0_1, is_lc, ctx->id("OFX0"));
607 if (slice0 == nullptr) {
608 if (!net_driven_by(ctx, ofx0_0, is_l6mux, ctx->id("Z")) &&
609 !net_driven_by(ctx, ofx0_0, is_lc, ctx->id("OFX1")))
610 log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
611 "('%s.%s')\n",
612 ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
613 ofx0_0->driver.port.c_str(ctx));
614 continue;
615 }
616 if (slice1 == nullptr) {
617 if (!net_driven_by(ctx, ofx0_1, is_l6mux, ctx->id("Z")) &&
618 !net_driven_by(ctx, ofx0_1, is_lc, ctx->id("OFX1")))
619 log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
620 "('%s.%s')\n",
621 ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
622 ofx0_0->driver.port.c_str(ctx));
623 continue;
624 }
625 if (ctx->verbose)
626 log_info(" mux '%s' forms part of a LUT6\n", cell.first.c_str(ctx));
627 replace_port(ci, ctx->id("D0"), slice1, id_FXA);
628 replace_port(ci, ctx->id("D1"), slice1, id_FXB);
629 replace_port(ci, ctx->id("SD"), slice1, id_M1);
630 replace_port(ci, ctx->id("Z"), slice1, id_OFX1);
631 slice0->constr_z = 1;
632 slice0->constr_x = 0;
633 slice0->constr_y = 0;
634 slice0->constr_parent = slice1;
635 slice1->constr_z = 0;
636 slice1->constr_abs_z = true;
637 slice1->constr_children.push_back(slice0);
638
639 if (lutffPairs.find(ci->name) != lutffPairs.end()) {
640 CellInfo *ff = ctx->cells.at(lutffPairs[ci->name]).get();
641 ff_to_slice(ctx, ff, slice1, 1, true);
642 packed_cells.insert(ff->name);
643 sliceUsage[slice1->name].ff1_used = true;
644 lutffPairs.erase(ci->name);
645 fflutPairs.erase(ff->name);
646 }
647
648 packed_cells.insert(ci->name);
649 }
650 }
651 flush_cells();
652 // Pack LUT7s
653 for (auto cell : sorted(ctx->cells)) {
654 CellInfo *ci = cell.second;
655 if (is_l6mux(ctx, ci)) {
656 NetInfo *ofx1_0 = ci->ports.at(ctx->id("D0")).net;
657 if (ofx1_0 == nullptr)
658 log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
659 NetInfo *ofx1_1 = ci->ports.at(ctx->id("D1")).net;
660 if (ofx1_1 == nullptr)
661 log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
662 CellInfo *slice1 = net_driven_by(ctx, ofx1_0, is_lc, ctx->id("OFX1"));
663 CellInfo *slice3 = net_driven_by(ctx, ofx1_1, is_lc, ctx->id("OFX1"));
664 if (slice1 == nullptr)
665 log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX ('%s.%s')\n",
666 ci->name.c_str(ctx), ofx1_0->driver.cell->name.c_str(ctx),
667 ofx1_0->driver.port.c_str(ctx));
668 if (slice3 == nullptr)
669 log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX ('%s.%s')\n",
670 ci->name.c_str(ctx), ofx1_1->driver.cell->name.c_str(ctx),
671 ofx1_1->driver.port.c_str(ctx));
672
673 NetInfo *fxa_0 = slice1->ports.at(id_FXA).net;
674 if (fxa_0 == nullptr)
675 log_error("SLICE '%s' has disconnected port 'FXA'\n", slice1->name.c_str(ctx));
676 NetInfo *fxa_1 = slice3->ports.at(id_FXA).net;
677 if (fxa_1 == nullptr)
678 log_error("SLICE '%s' has disconnected port 'FXA'\n", slice3->name.c_str(ctx));
679
680 CellInfo *slice0 = net_driven_by(ctx, fxa_0, is_lc, ctx->id("OFX0"));
681 CellInfo *slice2 = net_driven_by(ctx, fxa_1, is_lc, ctx->id("OFX0"));
682 if (slice0 == nullptr)
683 log_error("SLICE '%s' has FXA driven by cell other than a SLICE OFX0 ('%s.%s')\n",
684 slice1->name.c_str(ctx), fxa_0->driver.cell->name.c_str(ctx),
685 fxa_0->driver.port.c_str(ctx));
686 if (slice2 == nullptr)
687 log_error("SLICE '%s' has FXA driven by cell other than a SLICE OFX0 ('%s.%s')\n",
688 slice3->name.c_str(ctx), fxa_1->driver.cell->name.c_str(ctx),
689 fxa_1->driver.port.c_str(ctx));
690
691 replace_port(ci, ctx->id("D0"), slice2, id_FXA);
692 replace_port(ci, ctx->id("D1"), slice2, id_FXB);
693 replace_port(ci, ctx->id("SD"), slice2, id_M1);
694 replace_port(ci, ctx->id("Z"), slice2, id_OFX1);
695
696 for (auto slice : {slice0, slice1, slice2, slice3}) {
697 slice->constr_children.clear();
698 slice->constr_abs_z = false;
699 slice->constr_x = slice->UNCONSTR;
700 slice->constr_y = slice->UNCONSTR;
701 slice->constr_z = slice->UNCONSTR;
702 slice->constr_parent = nullptr;
703 }
704 slice3->constr_children.clear();
705 slice3->constr_abs_z = true;
706 slice3->constr_z = 0;
707
708 slice2->constr_children.clear();
709 slice2->constr_abs_z = true;
710 slice2->constr_z = 1;
711 slice2->constr_x = 0;
712 slice2->constr_y = 0;
713 slice2->constr_parent = slice3;
714 slice3->constr_children.push_back(slice2);
715
716 slice1->constr_children.clear();
717 slice1->constr_abs_z = true;
718 slice1->constr_z = 2;
719 slice1->constr_x = 0;
720 slice1->constr_y = 0;
721 slice1->constr_parent = slice3;
722 slice3->constr_children.push_back(slice1);
723
724 slice0->constr_children.clear();
725 slice0->constr_abs_z = true;
726 slice0->constr_z = 3;
727 slice0->constr_x = 0;
728 slice0->constr_y = 0;
729 slice0->constr_parent = slice3;
730 slice3->constr_children.push_back(slice0);
731
732 if (lutffPairs.find(ci->name) != lutffPairs.end()) {
733 CellInfo *ff = ctx->cells.at(lutffPairs[ci->name]).get();
734 ff_to_slice(ctx, ff, slice2, 1, true);
735 packed_cells.insert(ff->name);
736 sliceUsage[slice2->name].ff1_used = true;
737 lutffPairs.erase(ci->name);
738 fflutPairs.erase(ff->name);
739 }
740
741 packed_cells.insert(ci->name);
742 }
743 }
744 flush_cells();
745 }
746 // Create a feed in to the carry chain
make_carry_feed_in(NetInfo * carry,PortRef chain_in)747 CellInfo *make_carry_feed_in(NetInfo *carry, PortRef chain_in)
748 {
749 std::unique_ptr<CellInfo> feedin = create_ecp5_cell(ctx, ctx->id("CCU2C"));
750
751 feedin->params[ctx->id("INIT0")] = Property(10, 16); // LUT4 = 0; LUT2 = A
752 feedin->params[ctx->id("INIT1")] = Property(65535, 16);
753 feedin->params[ctx->id("INJECT1_0")] = std::string("NO");
754 feedin->params[ctx->id("INJECT1_1")] = std::string("YES");
755
756 carry->users.erase(std::remove_if(carry->users.begin(), carry->users.end(),
757 [chain_in](const PortRef &user) {
758 return user.port == chain_in.port && user.cell == chain_in.cell;
759 }),
760 carry->users.end());
761 connect_port(ctx, carry, feedin.get(), id_A0);
762
763 std::unique_ptr<NetInfo> new_carry(new NetInfo());
764 new_carry->name = ctx->id(feedin->name.str(ctx) + "$COUT");
765 connect_port(ctx, new_carry.get(), feedin.get(), ctx->id("COUT"));
766 chain_in.cell->ports[chain_in.port].net = nullptr;
767 connect_port(ctx, new_carry.get(), chain_in.cell, chain_in.port);
768
769 CellInfo *feedin_ptr = feedin.get();
770 IdString feedin_name = feedin->name;
771 ctx->cells[feedin_name] = std::move(feedin);
772 IdString new_carry_name = new_carry->name;
773 ctx->nets[new_carry_name] = std::move(new_carry);
774 return feedin_ptr;
775 }
776
777 // Create a feed out and loop through from the carry chain
make_carry_feed_out(NetInfo * carry,boost::optional<PortRef> chain_next=boost::optional<PortRef> ())778 CellInfo *make_carry_feed_out(NetInfo *carry, boost::optional<PortRef> chain_next = boost::optional<PortRef>())
779 {
780 std::unique_ptr<CellInfo> feedout = create_ecp5_cell(ctx, ctx->id("CCU2C"));
781
782 feedout->params[ctx->id("INIT0")] = Property(0, 16);
783 feedout->params[ctx->id("INIT1")] = Property(10, 16); // LUT4 = 0; LUT2 = A
784 feedout->params[ctx->id("INJECT1_0")] = std::string("NO");
785 feedout->params[ctx->id("INJECT1_1")] = std::string("NO");
786
787 PortRef carry_drv = carry->driver;
788 carry->driver.cell = nullptr;
789 connect_port(ctx, carry, feedout.get(), ctx->id("S0"));
790
791 std::unique_ptr<NetInfo> new_cin(new NetInfo());
792 new_cin->name = ctx->id(feedout->name.str(ctx) + "$CIN");
793 new_cin->driver = carry_drv;
794 carry_drv.cell->ports.at(carry_drv.port).net = new_cin.get();
795 connect_port(ctx, new_cin.get(), feedout.get(), ctx->id("CIN"));
796
797 if (chain_next) {
798 // Loop back into LUT4_1 for feedthrough
799 connect_port(ctx, carry, feedout.get(), id_A1);
800
801 carry->users.erase(std::remove_if(carry->users.begin(), carry->users.end(),
802 [chain_next](const PortRef &user) {
803 return user.port == chain_next->port && user.cell == chain_next->cell;
804 }),
805 carry->users.end());
806
807 std::unique_ptr<NetInfo> new_cout(new NetInfo());
808 new_cout->name = ctx->id(feedout->name.str(ctx) + "$COUT");
809 connect_port(ctx, new_cout.get(), feedout.get(), ctx->id("COUT"));
810
811 chain_next->cell->ports[chain_next->port].net = nullptr;
812 connect_port(ctx, new_cout.get(), chain_next->cell, chain_next->port);
813
814 IdString new_cout_name = new_cout->name;
815 ctx->nets[new_cout_name] = std::move(new_cout);
816 }
817
818 CellInfo *feedout_ptr = feedout.get();
819 IdString feedout_name = feedout->name;
820 ctx->cells[feedout_name] = std::move(feedout);
821
822 IdString new_cin_name = new_cin->name;
823 ctx->nets[new_cin_name] = std::move(new_cin);
824
825 return feedout_ptr;
826 }
827
828 // Split a carry chain into multiple legal chains
split_carry_chain(CellChain & carryc)829 std::vector<CellChain> split_carry_chain(CellChain &carryc)
830 {
831 bool start_of_chain = true;
832 std::vector<CellChain> chains;
833 const int max_length = (ctx->chip_info->width - 4) * 4 - 2;
834 auto curr_cell = carryc.cells.begin();
835 while (curr_cell != carryc.cells.end()) {
836 CellInfo *cell = *curr_cell;
837 if (start_of_chain) {
838 chains.emplace_back();
839 start_of_chain = false;
840 if (cell->ports.at(ctx->id("CIN")).net) {
841 // CIN is not constant and not part of a chain. Must feed in from fabric
842 PortRef inport;
843 inport.cell = cell;
844 inport.port = ctx->id("CIN");
845 CellInfo *feedin = make_carry_feed_in(cell->ports.at(ctx->id("CIN")).net, inport);
846 chains.back().cells.push_back(feedin);
847 }
848 }
849 chains.back().cells.push_back(cell);
850 bool split_chain = int(chains.back().cells.size()) > max_length;
851 if (split_chain) {
852 CellInfo *passout = make_carry_feed_out(cell->ports.at(ctx->id("COUT")).net);
853 chains.back().cells.back() = passout;
854 start_of_chain = true;
855 } else {
856 NetInfo *carry_net = cell->ports.at(ctx->id("COUT")).net;
857 bool at_end = (curr_cell == carryc.cells.end() - 1);
858 if (carry_net != nullptr && (carry_net->users.size() > 1 || at_end)) {
859 boost::optional<PortRef> nextport;
860 if (!at_end) {
861 auto next_cell = *(curr_cell + 1);
862 PortRef nextpr;
863 nextpr.cell = next_cell;
864 nextpr.port = ctx->id("CIN");
865 nextport = nextpr;
866 }
867 CellInfo *passout = make_carry_feed_out(cell->ports.at(ctx->id("COUT")).net, nextport);
868 chains.back().cells.push_back(passout);
869 }
870 ++curr_cell;
871 }
872 }
873 return chains;
874 }
875
876 // Pack carries and set up appropriate relative constraints
pack_carries()877 void pack_carries()
878 {
879 log_info("Packing carries...\n");
880 // Find all chains (including single carry cells)
881 auto carry_chains = find_chains(
882 ctx, [](const Context *ctx, const CellInfo *cell) { return is_carry(ctx, cell); },
883 [](const Context *ctx, const CellInfo *cell) {
884 return net_driven_by(ctx, cell->ports.at(ctx->id("CIN")).net, is_carry, ctx->id("COUT"));
885 },
886 [](const Context *ctx, const CellInfo *cell) {
887 return net_only_drives(ctx, cell->ports.at(ctx->id("COUT")).net, is_carry, ctx->id("CIN"), false);
888 },
889 1);
890 std::vector<CellChain> all_chains;
891
892 // Chain splitting
893 for (auto &base_chain : carry_chains) {
894 if (ctx->verbose) {
895 log_info("Found carry chain: \n");
896 for (auto entry : base_chain.cells)
897 log_info(" %s\n", entry->name.c_str(ctx));
898 log_info("\n");
899 }
900 std::vector<CellChain> split_chains = split_carry_chain(base_chain);
901 for (auto &chain : split_chains) {
902 all_chains.push_back(chain);
903 }
904 }
905
906 std::vector<std::vector<CellInfo *>> packed_chains;
907
908 // Chain packing
909 std::vector<std::tuple<CellInfo *, CellInfo *, int>> ff_packing;
910 for (auto &chain : all_chains) {
911 int cell_count = 0;
912 std::vector<CellInfo *> tile_ffs;
913 std::vector<CellInfo *> packed_chain;
914 for (auto &cell : chain.cells) {
915 if (cell_count % 4 == 0)
916 tile_ffs.clear();
917 std::unique_ptr<CellInfo> slice =
918 create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), cell->name.str(ctx) + "$CCU2_SLICE");
919
920 ccu2c_to_slice(ctx, cell, slice.get());
921
922 CellInfo *ff0 = nullptr;
923 NetInfo *f0net = slice->ports.at(ctx->id("F0")).net;
924 if (f0net != nullptr) {
925 ff0 = net_only_drives(ctx, f0net, is_ff, ctx->id("DI"), false);
926 if (ff0 != nullptr && can_add_ff_to_tile(tile_ffs, ff0)) {
927 ff_packing.push_back(std::make_tuple(ff0, slice.get(), 0));
928 tile_ffs.push_back(ff0);
929 packed_cells.insert(ff0->name);
930 }
931 }
932
933 CellInfo *ff1 = nullptr;
934 NetInfo *f1net = slice->ports.at(ctx->id("F1")).net;
935 if (f1net != nullptr) {
936 ff1 = net_only_drives(ctx, f1net, is_ff, ctx->id("DI"), false);
937 if (ff1 != nullptr && (ff0 == nullptr || can_pack_ffs(ff0, ff1)) &&
938 can_add_ff_to_tile(tile_ffs, ff1)) {
939 ff_packing.push_back(std::make_tuple(ff1, slice.get(), 1));
940 tile_ffs.push_back(ff1);
941 packed_cells.insert(ff1->name);
942 }
943 }
944 packed_chain.push_back(slice.get());
945 new_cells.push_back(std::move(slice));
946 packed_cells.insert(cell->name);
947 cell_count++;
948 }
949 packed_chains.push_back(packed_chain);
950 }
951
952 for (auto ff : ff_packing)
953 ff_to_slice(ctx, std::get<0>(ff), std::get<1>(ff), std::get<2>(ff), true);
954
955 // Relative chain placement
956 for (auto &chain : packed_chains) {
957 chain.at(0)->constr_abs_z = true;
958 chain.at(0)->constr_z = 0;
959 for (int i = 1; i < int(chain.size()); i++) {
960 chain.at(i)->constr_x = (i / 4);
961 chain.at(i)->constr_y = 0;
962 chain.at(i)->constr_z = i % 4;
963 chain.at(i)->constr_abs_z = true;
964 chain.at(i)->constr_parent = chain.at(0);
965 chain.at(0)->constr_children.push_back(chain.at(i));
966 }
967 }
968
969 flush_cells();
970 }
971
972 // Pack distributed RAM
pack_dram()973 void pack_dram()
974 {
975 for (auto cell : sorted(ctx->cells)) {
976 CellInfo *ci = cell.second;
977 if (is_dpram(ctx, ci)) {
978
979 // Create RAMW slice
980 std::unique_ptr<CellInfo> ramw_slice =
981 create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$RAMW_SLICE");
982 dram_to_ramw(ctx, ci, ramw_slice.get());
983
984 // Create actual RAM slices
985 std::unique_ptr<CellInfo> ram0_slice =
986 create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$DPRAM0_SLICE");
987 dram_to_ram_slice(ctx, ci, ram0_slice.get(), ramw_slice.get(), 0);
988
989 std::unique_ptr<CellInfo> ram1_slice =
990 create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$DPRAM1_SLICE");
991 dram_to_ram_slice(ctx, ci, ram1_slice.get(), ramw_slice.get(), 1);
992
993 // Disconnect ports of original cell after packing
994 disconnect_port(ctx, ci, id_WCK);
995 disconnect_port(ctx, ci, id_WRE);
996
997 disconnect_port(ctx, ci, ctx->id("RAD[0]"));
998 disconnect_port(ctx, ci, ctx->id("RAD[1]"));
999 disconnect_port(ctx, ci, ctx->id("RAD[2]"));
1000 disconnect_port(ctx, ci, ctx->id("RAD[3]"));
1001
1002 // Attempt to pack FFs into RAM slices
1003 std::vector<std::tuple<CellInfo *, CellInfo *, int>> ff_packing;
1004 std::vector<CellInfo *> tile_ffs;
1005 for (auto slice : {ram0_slice.get(), ram1_slice.get()}) {
1006 CellInfo *ff0 = nullptr;
1007 NetInfo *f0net = slice->ports.at(ctx->id("F0")).net;
1008 if (f0net != nullptr) {
1009 ff0 = net_only_drives(ctx, f0net, is_ff, ctx->id("DI"), false);
1010 if (ff0 != nullptr && can_add_ff_to_tile(tile_ffs, ff0)) {
1011 if (can_pack_ff_dram(slice, ff0)) {
1012 ff_packing.push_back(std::make_tuple(ff0, slice, 0));
1013 tile_ffs.push_back(ff0);
1014 packed_cells.insert(ff0->name);
1015 }
1016 }
1017 }
1018
1019 CellInfo *ff1 = nullptr;
1020 NetInfo *f1net = slice->ports.at(ctx->id("F1")).net;
1021 if (f1net != nullptr) {
1022 ff1 = net_only_drives(ctx, f1net, is_ff, ctx->id("DI"), false);
1023 if (ff1 != nullptr && (ff0 == nullptr || can_pack_ffs(ff0, ff1)) &&
1024 can_add_ff_to_tile(tile_ffs, ff1)) {
1025 if (can_pack_ff_dram(slice, ff1)) {
1026 ff_packing.push_back(std::make_tuple(ff1, slice, 1));
1027 tile_ffs.push_back(ff1);
1028 packed_cells.insert(ff1->name);
1029 }
1030 }
1031 }
1032 }
1033
1034 for (auto ff : ff_packing)
1035 ff_to_slice(ctx, std::get<0>(ff), std::get<1>(ff), std::get<2>(ff), true);
1036
1037 // Setup placement constraints
1038 ram0_slice->constr_abs_z = true;
1039 ram0_slice->constr_z = 0;
1040
1041 ram1_slice->constr_parent = ram0_slice.get();
1042 ram1_slice->constr_abs_z = true;
1043 ram1_slice->constr_x = 0;
1044 ram1_slice->constr_y = 0;
1045 ram1_slice->constr_z = 1;
1046 ram0_slice->constr_children.push_back(ram1_slice.get());
1047
1048 ramw_slice->constr_parent = ram0_slice.get();
1049 ramw_slice->constr_abs_z = true;
1050 ramw_slice->constr_x = 0;
1051 ramw_slice->constr_y = 0;
1052 ramw_slice->constr_z = 2;
1053 ram0_slice->constr_children.push_back(ramw_slice.get());
1054
1055 new_cells.push_back(std::move(ram0_slice));
1056 new_cells.push_back(std::move(ram1_slice));
1057 new_cells.push_back(std::move(ramw_slice));
1058 packed_cells.insert(ci->name);
1059 }
1060 }
1061 flush_cells();
1062 }
1063
1064 // Pack LUTs that have been paired together
pack_lut_pairs()1065 void pack_lut_pairs()
1066 {
1067 log_info("Packing paired LUTs into a SLICE...\n");
1068 for (auto pair : lutPairs) {
1069 CellInfo *lut0 = ctx->cells.at(pair.first).get();
1070 CellInfo *lut1 = ctx->cells.at(pair.second).get();
1071 std::unique_ptr<CellInfo> slice =
1072 create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), lut0->name.str(ctx) + "_SLICE");
1073
1074 lut_to_slice(ctx, lut0, slice.get(), 0);
1075 lut_to_slice(ctx, lut1, slice.get(), 1);
1076
1077 auto ff0 = lutffPairs.find(lut0->name);
1078
1079 if (ff0 != lutffPairs.end()) {
1080 ff_to_slice(ctx, ctx->cells.at(ff0->second).get(), slice.get(), 0, true);
1081 packed_cells.insert(ff0->second);
1082 fflutPairs.erase(ff0->second);
1083 lutffPairs.erase(lut0->name);
1084 }
1085
1086 auto ff1 = lutffPairs.find(lut1->name);
1087
1088 if (ff1 != lutffPairs.end()) {
1089 ff_to_slice(ctx, ctx->cells.at(ff1->second).get(), slice.get(), 1, true);
1090 packed_cells.insert(ff1->second);
1091 fflutPairs.erase(ff1->second);
1092 lutffPairs.erase(lut1->name);
1093 }
1094
1095 new_cells.push_back(std::move(slice));
1096 packed_cells.insert(lut0->name);
1097 packed_cells.insert(lut1->name);
1098 }
1099 flush_cells();
1100 }
1101
1102 // Pack single LUTs that weren't paired into their own slice,
1103 // with an optional FF also
pack_remaining_luts()1104 void pack_remaining_luts()
1105 {
1106 log_info("Packing unpaired LUTs into a SLICE...\n");
1107 for (auto cell : sorted(ctx->cells)) {
1108 CellInfo *ci = cell.second;
1109 if (is_lut(ctx, ci)) {
1110 std::unique_ptr<CellInfo> slice =
1111 create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
1112 lut_to_slice(ctx, ci, slice.get(), 1);
1113 auto ff = lutffPairs.find(ci->name);
1114
1115 if (ff != lutffPairs.end()) {
1116 ff_to_slice(ctx, ctx->cells.at(ff->second).get(), slice.get(), 1, true);
1117 packed_cells.insert(ff->second);
1118 fflutPairs.erase(ff->second);
1119 lutffPairs.erase(ci->name);
1120 }
1121
1122 new_cells.push_back(std::move(slice));
1123 packed_cells.insert(ci->name);
1124 }
1125 }
1126 flush_cells();
1127 }
1128
1129 // Find a cell that meets some criterea near an origin cell
1130 // Used for packing an FF into a nearby SLICE
find_nearby_cell(CellInfo * origin,TFunc Func)1131 template <typename TFunc> CellInfo *find_nearby_cell(CellInfo *origin, TFunc Func)
1132 {
1133 std::unordered_set<CellInfo *> visited_cells;
1134 std::queue<CellInfo *> to_visit;
1135 visited_cells.insert(origin);
1136 to_visit.push(origin);
1137 int iter = 0;
1138 while (!to_visit.empty() && iter < 10000) {
1139 CellInfo *cursor = to_visit.front();
1140 to_visit.pop();
1141 if (Func(cursor))
1142 return cursor;
1143 for (const auto &port : cursor->ports) {
1144 NetInfo *pn = port.second.net;
1145 if (pn == nullptr)
1146 continue;
1147 // Skip high-fanout nets that are unlikely to be relevant
1148 if (pn->users.size() > 25)
1149 continue;
1150 // Add other ports on this net if not already visited
1151 auto visit_port = [&](const PortRef &port) {
1152 if (port.cell == nullptr)
1153 return;
1154 if (visited_cells.count(port.cell))
1155 return;
1156 // If not already visited; add the cell of this port to the queue
1157 to_visit.push(port.cell);
1158 visited_cells.insert(port.cell);
1159 };
1160 visit_port(pn->driver);
1161 for (const auto &usr : pn->users)
1162 visit_port(usr);
1163 }
1164 ++iter;
1165 }
1166 return nullptr;
1167 }
1168
1169 // Pack flipflops that weren't paired with a LUT
1170 float dense_pack_mode_thresh = 0.95f;
pack_remaining_ffs()1171 void pack_remaining_ffs()
1172 {
1173 // Enter dense flipflop packing mode once utilisation exceeds a threshold (default: 95%)
1174 int used_slices = 0;
1175 for (auto &cell : ctx->cells)
1176 if (cell.second->type == id_TRELLIS_SLICE)
1177 ++used_slices;
1178
1179 log_info("Packing unpaired FFs into a SLICE...\n");
1180 for (auto cell : sorted(ctx->cells)) {
1181 CellInfo *ci = cell.second;
1182 if (is_ff(ctx, ci)) {
1183 bool pack_dense = used_slices > (dense_pack_mode_thresh * available_slices);
1184 bool requires_m = get_net_or_empty(ci, ctx->id("M")) != nullptr;
1185 if (pack_dense && !requires_m) {
1186 // If dense packing threshold exceeded; always try and pack the FF into an existing slice
1187 // Find a SLICE with space "near" the flipflop in the netlist
1188 std::vector<CellInfo *> ltile;
1189 CellInfo *target = find_nearby_cell(ci, [&](CellInfo *cursor) {
1190 if (cursor->type != id_TRELLIS_SLICE)
1191 return false;
1192 if (!cursor->constr_children.empty() || cursor->constr_parent != nullptr) {
1193 auto &constr_children = (cursor->constr_parent != nullptr)
1194 ? cursor->constr_parent->constr_children
1195 : cursor->constr_children;
1196 // Skip big chains for performance
1197 if (constr_children.size() > 8)
1198 return false;
1199 // Have to check the whole of the tile for legality when dealing with chains, not just slice
1200 ltile.clear();
1201 if (cursor->constr_parent != nullptr)
1202 ltile.push_back(cursor->constr_parent);
1203 else
1204 ltile.push_back(cursor);
1205 for (auto c : constr_children)
1206 ltile.push_back(c);
1207 if (!can_add_ff_to_tile(ltile, cursor))
1208 return false;
1209 }
1210 if (!can_add_ff_to_slice(cursor, ci))
1211 return false;
1212 for (int i = 0; i < 2; i++)
1213 if (is_ff_available(cursor, i))
1214 return true;
1215 return false;
1216 });
1217
1218 // If found, add the FF to this slice instead of creating a new one
1219 if (target != nullptr) {
1220 for (int i = 0; i < 2; i++) {
1221 if (is_ff_available(target, i)) {
1222 ff_to_slice(ctx, ci, target, i, false);
1223 goto ff_packed;
1224 }
1225 }
1226 }
1227
1228 if (false) {
1229 ff_packed:
1230 packed_cells.insert(ci->name);
1231 continue;
1232 }
1233 }
1234
1235 std::unique_ptr<CellInfo> slice =
1236 create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
1237 ff_to_slice(ctx, ci, slice.get(), 0, false);
1238 new_cells.push_back(std::move(slice));
1239 ++used_slices;
1240 packed_cells.insert(ci->name);
1241 }
1242 }
1243 flush_cells();
1244 }
1245
make_init_with_const_input(int init,int input,bool value)1246 int make_init_with_const_input(int init, int input, bool value)
1247 {
1248 int new_init = 0;
1249 for (int i = 0; i < 16; i++) {
1250 if (((i >> input) & 0x1) != value) {
1251 int other_i = (i & (~(1 << input))) | (value << input);
1252 if ((init >> other_i) & 0x1)
1253 new_init |= (1 << i);
1254 } else {
1255 if ((init >> i) & 0x1)
1256 new_init |= (1 << i);
1257 }
1258 }
1259 return new_init;
1260 }
1261
set_lut_input_constant(CellInfo * cell,IdString input,bool value)1262 void set_lut_input_constant(CellInfo *cell, IdString input, bool value)
1263 {
1264 int index = std::string("ABCD").find(input.str(ctx));
1265 int init = int_or_default(cell->params, ctx->id("INIT"));
1266 int new_init = make_init_with_const_input(init, index, value);
1267 cell->params[ctx->id("INIT")] = Property(new_init, 16);
1268 cell->ports.at(input).net = nullptr;
1269 }
1270
set_ccu2c_input_constant(CellInfo * cell,IdString input,bool value)1271 void set_ccu2c_input_constant(CellInfo *cell, IdString input, bool value)
1272 {
1273 std::string input_str = input.str(ctx);
1274 int lut = std::stoi(input_str.substr(1));
1275 int index = std::string("ABCD").find(input_str[0]);
1276 int init = int_or_default(cell->params, ctx->id("INIT" + std::to_string(lut)));
1277 int new_init = make_init_with_const_input(init, index, value);
1278 cell->params[ctx->id("INIT" + std::to_string(lut))] = Property(new_init, 16);
1279 cell->ports.at(input).net = nullptr;
1280 }
1281
is_ccu2c_port_high(CellInfo * cell,IdString input)1282 bool is_ccu2c_port_high(CellInfo *cell, IdString input)
1283 {
1284 if (!cell->ports.count(input))
1285 return true; // disconnected port is high
1286 if (cell->ports.at(input).net == nullptr || cell->ports.at(input).net->name == ctx->id("$PACKER_VCC_NET"))
1287 return true; // disconnected or tied-high port
1288 if (cell->ports.at(input).net->driver.cell != nullptr &&
1289 cell->ports.at(input).net->driver.cell->type == ctx->id("VCC"))
1290 return true; // pre-pack high
1291 return false;
1292 }
1293
1294 // Merge a net into a constant net
set_net_constant(const Context * ctx,NetInfo * orig,NetInfo * constnet,bool constval)1295 void set_net_constant(const Context *ctx, NetInfo *orig, NetInfo *constnet, bool constval)
1296 {
1297 orig->driver.cell = nullptr;
1298 for (auto user : orig->users) {
1299 if (user.cell != nullptr) {
1300 CellInfo *uc = user.cell;
1301 if (ctx->verbose)
1302 log_info("%s user %s\n", orig->name.c_str(ctx), uc->name.c_str(ctx));
1303 if (is_lut(ctx, uc)) {
1304 set_lut_input_constant(uc, user.port, constval);
1305 } else if (is_ff(ctx, uc) && user.port == ctx->id("CE")) {
1306 uc->params[ctx->id("CEMUX")] = std::string(constval ? "1" : "0");
1307 uc->ports[user.port].net = nullptr;
1308 } else if (is_carry(ctx, uc)) {
1309 if (constval &&
1310 (user.port == id_A0 || user.port == id_A1 || user.port == id_B0 || user.port == id_B1 ||
1311 user.port == id_C0 || user.port == id_C1 || user.port == id_D0 || user.port == id_D1)) {
1312 // Input tied high, nothing special to do (bitstream gen will auto-enable tie-high)
1313 uc->ports[user.port].net = nullptr;
1314 } else if (!constval) {
1315 if (user.port == id_A0 || user.port == id_A1 || user.port == id_B0 || user.port == id_B1) {
1316 // These inputs can be switched to tie-high without consequence
1317 set_ccu2c_input_constant(uc, user.port, constval);
1318 } else if (user.port == id_C0 && is_ccu2c_port_high(uc, id_D0)) {
1319 // Partner must be tied high
1320 set_ccu2c_input_constant(uc, user.port, constval);
1321 } else if (user.port == id_D0 && is_ccu2c_port_high(uc, id_C0)) {
1322 // Partner must be tied high
1323 set_ccu2c_input_constant(uc, user.port, constval);
1324 } else if (user.port == id_C1 && is_ccu2c_port_high(uc, id_D1)) {
1325 // Partner must be tied high
1326 set_ccu2c_input_constant(uc, user.port, constval);
1327 } else if (user.port == id_D1 && is_ccu2c_port_high(uc, id_C1)) {
1328 // Partner must be tied high
1329 set_ccu2c_input_constant(uc, user.port, constval);
1330 } else {
1331 // Not allowed to change to a tie-high
1332 uc->ports[user.port].net = constnet;
1333 constnet->users.push_back(user);
1334 }
1335 } else {
1336 uc->ports[user.port].net = constnet;
1337 constnet->users.push_back(user);
1338 }
1339 } else if (is_ff(ctx, uc) && user.port == ctx->id("LSR") &&
1340 ((!constval && str_or_default(uc->params, ctx->id("LSRMUX"), "LSR") == "LSR") ||
1341 (constval && str_or_default(uc->params, ctx->id("LSRMUX"), "LSR") == "INV"))) {
1342 uc->ports[user.port].net = nullptr;
1343 } else if (uc->type == id_DP16KD) {
1344 if (user.port == id_CLKA || user.port == id_CLKB || user.port == id_RSTA || user.port == id_RSTB ||
1345 user.port == id_WEA || user.port == id_WEB || user.port == id_CEA || user.port == id_CEB ||
1346 user.port == id_OCEA || user.port == id_OCEB || user.port == id_CSA0 || user.port == id_CSA1 ||
1347 user.port == id_CSA2 || user.port == id_CSB0 || user.port == id_CSB1 || user.port == id_CSB2) {
1348 // Connect to CIB CLK, LSR or CE. Default state is 1
1349 uc->params[ctx->id(user.port.str(ctx) + "MUX")] = constval ? user.port.str(ctx) : "INV";
1350 } else {
1351 // Connected to CIB ABCD. Default state is bitstream configurable
1352 uc->params[ctx->id(user.port.str(ctx) + "MUX")] = std::string(constval ? "1" : "0");
1353 }
1354 uc->ports[user.port].net = nullptr;
1355 } else if (uc->type == id_ALU54B || uc->type == id_MULT18X18D) {
1356 if (user.port.str(ctx).substr(0, 3) == "CLK" || user.port.str(ctx).substr(0, 2) == "CE" ||
1357 user.port.str(ctx).substr(0, 3) == "RST" || user.port.str(ctx).substr(0, 3) == "SRO" ||
1358 user.port.str(ctx).substr(0, 3) == "SRI" || user.port.str(ctx).substr(0, 2) == "RO" ||
1359 user.port.str(ctx).substr(0, 2) == "MA" || user.port.str(ctx).substr(0, 2) == "MB" ||
1360 user.port.str(ctx).substr(0, 3) == "CFB" || user.port.str(ctx).substr(0, 3) == "CIN" ||
1361 user.port.str(ctx).substr(0, 6) == "SOURCE" || user.port.str(ctx).substr(0, 6) == "SIGNED" ||
1362 user.port.str(ctx).substr(0, 2) == "OP") {
1363 uc->ports[user.port].net = constnet;
1364 constnet->users.push_back(user);
1365 } else {
1366 // Connected to CIB ABCD. Default state is bitstream configurable
1367 uc->params[ctx->id(user.port.str(ctx) + "MUX")] = std::string(constval ? "1" : "0");
1368 uc->ports[user.port].net = nullptr;
1369 }
1370 } else {
1371 uc->ports[user.port].net = constnet;
1372 constnet->users.push_back(user);
1373 }
1374 }
1375 }
1376 orig->users.clear();
1377 }
1378
1379 // Pack constants (simple implementation)
pack_constants()1380 void pack_constants()
1381 {
1382 log_info("Packing constants..\n");
1383
1384 std::unique_ptr<CellInfo> gnd_cell = create_ecp5_cell(ctx, ctx->id("LUT4"), "$PACKER_GND");
1385 gnd_cell->params[ctx->id("INIT")] = Property(0, 16);
1386 std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
1387 gnd_net->name = ctx->id("$PACKER_GND_NET");
1388 gnd_net->driver.cell = gnd_cell.get();
1389 gnd_net->driver.port = ctx->id("Z");
1390 gnd_cell->ports.at(ctx->id("Z")).net = gnd_net.get();
1391
1392 std::unique_ptr<CellInfo> vcc_cell = create_ecp5_cell(ctx, ctx->id("LUT4"), "$PACKER_VCC");
1393 vcc_cell->params[ctx->id("INIT")] = Property(65535, 16);
1394 std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
1395 vcc_net->name = ctx->id("$PACKER_VCC_NET");
1396 vcc_net->driver.cell = vcc_cell.get();
1397 vcc_net->driver.port = ctx->id("Z");
1398 vcc_cell->ports.at(ctx->id("Z")).net = vcc_net.get();
1399
1400 std::vector<IdString> dead_nets;
1401
1402 bool gnd_used = false, vcc_used = false;
1403
1404 for (auto net : sorted(ctx->nets)) {
1405 NetInfo *ni = net.second;
1406 if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) {
1407 IdString drv_cell = ni->driver.cell->name;
1408 set_net_constant(ctx, ni, gnd_net.get(), false);
1409 gnd_used = true;
1410 dead_nets.push_back(net.first);
1411 ctx->cells.erase(drv_cell);
1412 } else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) {
1413 IdString drv_cell = ni->driver.cell->name;
1414 set_net_constant(ctx, ni, vcc_net.get(), true);
1415 vcc_used = true;
1416 dead_nets.push_back(net.first);
1417 ctx->cells.erase(drv_cell);
1418 }
1419 }
1420
1421 if (gnd_used) {
1422 ctx->cells[gnd_cell->name] = std::move(gnd_cell);
1423 ctx->nets[gnd_net->name] = std::move(gnd_net);
1424 }
1425 if (vcc_used) {
1426 ctx->cells[vcc_cell->name] = std::move(vcc_cell);
1427 ctx->nets[vcc_net->name] = std::move(vcc_net);
1428 }
1429
1430 for (auto dn : dead_nets) {
1431 ctx->nets.erase(dn);
1432 }
1433 }
1434
autocreate_empty_port(CellInfo * cell,IdString port)1435 void autocreate_empty_port(CellInfo *cell, IdString port)
1436 {
1437 if (!cell->ports.count(port)) {
1438 cell->ports[port].name = port;
1439 cell->ports[port].net = nullptr;
1440 cell->ports[port].type = PORT_IN;
1441 }
1442 }
1443
1444 // Pack EBR
pack_ebr()1445 void pack_ebr()
1446 {
1447 // Autoincrement WID (starting from 3 seems to match vendor behaviour?)
1448 int wid = 3;
1449 auto rename_bus = [&](CellInfo *c, const std::string &oldname, const std::string &newname, int width,
1450 int oldoffset, int newoffset) {
1451 for (int i = 0; i < width; i++)
1452 rename_port(ctx, c, ctx->id(oldname + std::to_string(i + oldoffset)),
1453 ctx->id(newname + std::to_string(i + newoffset)));
1454 };
1455 auto rename_param = [&](CellInfo *c, const std::string &oldname, const std::string &newname) {
1456 IdString o = ctx->id(oldname), n = ctx->id(newname);
1457 if (!c->params.count(o))
1458 return;
1459 c->params[n] = c->params[o];
1460 c->params.erase(o);
1461 };
1462 for (auto cell : sorted(ctx->cells)) {
1463 CellInfo *ci = cell.second;
1464 // Convert 36-bit PDP RAMs to regular 18-bit DP ones that match the Bel
1465 if (ci->type == ctx->id("PDPW16KD")) {
1466 ci->params[ctx->id("DATA_WIDTH_A")] = 36; // force PDP mode
1467 ci->params.erase(ctx->id("DATA_WIDTH_W"));
1468 rename_bus(ci, "BE", "ADA", 4, 0, 0);
1469 rename_bus(ci, "ADW", "ADA", 9, 0, 5);
1470 rename_bus(ci, "ADR", "ADB", 14, 0, 0);
1471 rename_bus(ci, "CSW", "CSA", 3, 0, 0);
1472 rename_bus(ci, "CSR", "CSB", 3, 0, 0);
1473 rename_bus(ci, "DI", "DIA", 18, 0, 0);
1474 rename_bus(ci, "DI", "DIB", 18, 18, 0);
1475 rename_bus(ci, "DO", "DOA", 18, 18, 0);
1476 rename_bus(ci, "DO", "DOB", 18, 0, 0);
1477 rename_port(ctx, ci, ctx->id("CLKW"), ctx->id("CLKA"));
1478 rename_port(ctx, ci, ctx->id("CLKR"), ctx->id("CLKB"));
1479 rename_port(ctx, ci, ctx->id("CEW"), ctx->id("CEA"));
1480 rename_port(ctx, ci, ctx->id("CER"), ctx->id("CEB"));
1481 rename_port(ctx, ci, ctx->id("OCER"), ctx->id("OCEB"));
1482 rename_param(ci, "CLKWMUX", "CLKAMUX");
1483 if (str_or_default(ci->params, ctx->id("CLKAMUX")) == "CLKW")
1484 ci->params[ctx->id("CLKAMUX")] = std::string("CLKA");
1485 if (str_or_default(ci->params, ctx->id("CLKBMUX")) == "CLKR")
1486 ci->params[ctx->id("CLKBMUX")] = std::string("CLKB");
1487 rename_param(ci, "CLKRMUX", "CLKRMUX");
1488 rename_param(ci, "CSDECODE_W", "CSDECODE_A");
1489 rename_param(ci, "CSDECODE_R", "CSDECODE_B");
1490 rename_param(ci, "REGMODE", "REGMODE_B");
1491 rename_param(ci, "DATA_WIDTH_R", "DATA_WIDTH_B");
1492 if (ci->ports.count(id_RST)) {
1493 autocreate_empty_port(ci, id_RSTA);
1494 autocreate_empty_port(ci, id_RSTB);
1495 NetInfo *rst = ci->ports.at(id_RST).net;
1496 connect_port(ctx, rst, ci, id_RSTA);
1497 connect_port(ctx, rst, ci, id_RSTB);
1498 disconnect_port(ctx, ci, id_RST);
1499 ci->ports.erase(id_RST);
1500 }
1501 ci->type = id_DP16KD;
1502 }
1503 }
1504 for (auto cell : sorted(ctx->cells)) {
1505 CellInfo *ci = cell.second;
1506 if (ci->type == id_DP16KD) {
1507 // Add ports, even if disconnected, to ensure correct tie-offs
1508 for (int i = 0; i < 14; i++) {
1509 autocreate_empty_port(ci, ctx->id("ADA" + std::to_string(i)));
1510 autocreate_empty_port(ci, ctx->id("ADB" + std::to_string(i)));
1511 }
1512 for (int i = 0; i < 18; i++) {
1513 autocreate_empty_port(ci, ctx->id("DIA" + std::to_string(i)));
1514 autocreate_empty_port(ci, ctx->id("DIB" + std::to_string(i)));
1515 }
1516 for (int i = 0; i < 3; i++) {
1517 autocreate_empty_port(ci, ctx->id("CSA" + std::to_string(i)));
1518 autocreate_empty_port(ci, ctx->id("CSB" + std::to_string(i)));
1519 }
1520 for (int i = 0; i < 3; i++) {
1521 autocreate_empty_port(ci, ctx->id("CSA" + std::to_string(i)));
1522 autocreate_empty_port(ci, ctx->id("CSB" + std::to_string(i)));
1523 }
1524
1525 autocreate_empty_port(ci, id_CLKA);
1526 autocreate_empty_port(ci, id_CEA);
1527 autocreate_empty_port(ci, id_OCEA);
1528 autocreate_empty_port(ci, id_WEA);
1529 autocreate_empty_port(ci, id_RSTA);
1530
1531 autocreate_empty_port(ci, id_CLKB);
1532 autocreate_empty_port(ci, id_CEB);
1533 autocreate_empty_port(ci, id_OCEB);
1534 autocreate_empty_port(ci, id_WEB);
1535 autocreate_empty_port(ci, id_RSTB);
1536
1537 ci->attrs[ctx->id("WID")] = wid++;
1538 }
1539 }
1540 }
1541
1542 // Pack DSPs
pack_dsps()1543 void pack_dsps()
1544 {
1545 for (auto cell : sorted(ctx->cells)) {
1546 CellInfo *ci = cell.second;
1547 if (ci->type == id_MULT18X18D) {
1548 // Add ports, even if disconnected, to ensure correct tie-offs
1549 for (auto sig : {"CLK", "CE", "RST"})
1550 for (int i = 0; i < 4; i++)
1551 autocreate_empty_port(ci, ctx->id(sig + std::to_string(i)));
1552 for (auto sig : {"SIGNED", "SOURCE"})
1553 for (auto c : {"A", "B"})
1554 autocreate_empty_port(ci, ctx->id(sig + std::string(c)));
1555 for (auto port : {"A", "B", "C"})
1556 for (int i = 0; i < 18; i++)
1557 autocreate_empty_port(ci, ctx->id(port + std::to_string(i)));
1558 for (auto port : {"SRIA", "SRIB"})
1559 for (int i = 0; i < 18; i++)
1560 autocreate_empty_port(ci, ctx->id(port + std::to_string(i)));
1561 } else if (ci->type == id_ALU54B) {
1562 for (auto sig : {"CLK", "CE", "RST"})
1563 for (int i = 0; i < 4; i++)
1564 autocreate_empty_port(ci, ctx->id(sig + std::to_string(i)));
1565 autocreate_empty_port(ci, id_SIGNEDIA);
1566 autocreate_empty_port(ci, id_SIGNEDIB);
1567 autocreate_empty_port(ci, id_SIGNEDCIN);
1568 for (auto port : {"A", "B", "MA", "MB"})
1569 for (int i = 0; i < 36; i++)
1570 autocreate_empty_port(ci, ctx->id(port + std::to_string(i)));
1571 for (auto port : {"C", "CFB", "CIN"})
1572 for (int i = 0; i < 54; i++)
1573 autocreate_empty_port(ci, ctx->id(port + std::to_string(i)));
1574 for (int i = 0; i < 11; i++)
1575 autocreate_empty_port(ci, ctx->id("OP" + std::to_string(i)));
1576 }
1577 }
1578 }
1579
1580 // "Pack" DCUs
pack_dcus()1581 void pack_dcus()
1582 {
1583 for (auto cell : sorted(ctx->cells)) {
1584 CellInfo *ci = cell.second;
1585 if (ci->type == id_DCUA) {
1586 if (ci->attrs.count(ctx->id("LOC"))) {
1587 std::string loc = ci->attrs.at(ctx->id("LOC")).as_string();
1588 if (loc == "DCU0" &&
1589 (ctx->args.type == ArchArgs::LFE5UM_25F || ctx->args.type == ArchArgs::LFE5UM5G_25F))
1590 ci->attrs[ctx->id("BEL")] = std::string("X42/Y50/DCU");
1591 else if (loc == "DCU0" &&
1592 (ctx->args.type == ArchArgs::LFE5UM_45F || ctx->args.type == ArchArgs::LFE5UM5G_45F))
1593 ci->attrs[ctx->id("BEL")] = std::string("X42/Y71/DCU");
1594 else if (loc == "DCU1" &&
1595 (ctx->args.type == ArchArgs::LFE5UM_45F || ctx->args.type == ArchArgs::LFE5UM5G_45F))
1596 ci->attrs[ctx->id("BEL")] = std::string("X69/Y71/DCU");
1597 else if (loc == "DCU0" &&
1598 (ctx->args.type == ArchArgs::LFE5UM_85F || ctx->args.type == ArchArgs::LFE5UM5G_85F))
1599 ci->attrs[ctx->id("BEL")] = std::string("X46/Y95/DCU");
1600 else if (loc == "DCU1" &&
1601 (ctx->args.type == ArchArgs::LFE5UM_85F || ctx->args.type == ArchArgs::LFE5UM5G_85F))
1602 ci->attrs[ctx->id("BEL")] = std::string("X71/Y95/DCU");
1603 else
1604 log_error("no DCU location '%s' in device '%s'\n", loc.c_str(), ctx->getChipName().c_str());
1605 }
1606 if (!ci->attrs.count(ctx->id("BEL")))
1607 log_error("DCU must be constrained to a Bel!\n");
1608 // Empty port auto-creation to generate correct tie-downs
1609 BelId exemplar_bel;
1610 for (auto bel : ctx->getBels()) {
1611 if (ctx->getBelType(bel) == id_DCUA) {
1612 exemplar_bel = bel;
1613 break;
1614 }
1615 }
1616 NPNR_ASSERT(exemplar_bel != BelId());
1617 for (auto pin : ctx->getBelPins(exemplar_bel))
1618 if (ctx->getBelPinType(exemplar_bel, pin) == PORT_IN)
1619 autocreate_empty_port(ci, pin);
1620 // Disconnect these ports if connected to constant to prevent routing failure
1621 for (auto ndport : {id_D_TXBIT_CLKP_FROM_ND, id_D_TXBIT_CLKN_FROM_ND, id_D_SYNC_ND,
1622 id_D_TXPLL_LOL_FROM_ND, id_CH0_HDINN, id_CH0_HDINP, id_CH1_HDINN, id_CH1_HDINP}) {
1623 const NetInfo *net = get_net_or_empty(ci, ndport);
1624 if (net == nullptr || net->driver.cell == nullptr)
1625 continue;
1626 IdString ct = net->driver.cell->type;
1627 if (ct == ctx->id("GND") || ct == ctx->id("VCC")) {
1628 disconnect_port(ctx, ci, ndport);
1629 ci->ports.erase(ndport);
1630 }
1631 }
1632 }
1633 }
1634 for (auto cell : sorted(ctx->cells)) {
1635 CellInfo *ci = cell.second;
1636 if (ci->type == id_EXTREFB) {
1637 const NetInfo *refo = net_or_nullptr(ci, id_REFCLKO);
1638 CellInfo *dcu = nullptr;
1639 if (refo == nullptr)
1640 log_error("EXTREFB REFCLKO must not be unconnected\n");
1641 for (auto user : refo->users) {
1642 if (user.cell->type != id_DCUA)
1643 continue;
1644 if (dcu != nullptr && dcu != user.cell)
1645 log_error("EXTREFB REFCLKO must only drive a single DCUA\n");
1646 dcu = user.cell;
1647 }
1648 if (!dcu->attrs.count(ctx->id("BEL")))
1649 log_error("DCU must be constrained to a Bel!\n");
1650 std::string bel = dcu->attrs.at(ctx->id("BEL")).as_string();
1651 NPNR_ASSERT(bel.substr(bel.length() - 3) == "DCU");
1652 bel.replace(bel.length() - 3, 3, "EXTREF");
1653 ci->attrs[ctx->id("BEL")] = bel;
1654 } else if (ci->type == id_PCSCLKDIV) {
1655 const NetInfo *clki = net_or_nullptr(ci, id_CLKI);
1656 if (clki != nullptr && clki->driver.cell != nullptr && clki->driver.cell->type == id_DCUA) {
1657 CellInfo *dcu = clki->driver.cell;
1658 if (!dcu->attrs.count(ctx->id("BEL")))
1659 log_error("DCU must be constrained to a Bel!\n");
1660 BelId bel = ctx->getBelByName(ctx->id(dcu->attrs.at(ctx->id("BEL")).as_string()));
1661 if (bel == BelId())
1662 log_error("Invalid DCU bel '%s'\n", dcu->attrs.at(ctx->id("BEL")).c_str());
1663 Loc loc = ctx->getBelLocation(bel);
1664 // DCU0 -> CLKDIV z=0; DCU1 -> CLKDIV z=1
1665 ci->constr_abs_z = true;
1666 ci->constr_z = (loc.x >= 69) ? 1 : 0;
1667 }
1668 }
1669 }
1670 }
1671
1672 // Miscellaneous packer tasks
pack_misc()1673 void pack_misc()
1674 {
1675 for (auto cell : sorted(ctx->cells)) {
1676 CellInfo *ci = cell.second;
1677 if (ci->type == id_USRMCLK) {
1678 rename_port(ctx, ci, ctx->id("USRMCLKI"), id_PADDO);
1679 rename_port(ctx, ci, ctx->id("USRMCLKTS"), id_PADDT);
1680 rename_port(ctx, ci, ctx->id("USRMCLKO"), id_PADDI);
1681 } else if (ci->type == id_GSR || ci->type == ctx->id("SGSR")) {
1682 ci->params[ctx->id("MODE")] = std::string("ACTIVE_LOW");
1683 ci->params[ctx->id("SYNCMODE")] =
1684 ci->type == ctx->id("SGSR") ? std::string("SYNC") : std::string("ASYNC");
1685 ci->type = id_GSR;
1686 for (BelId bel : ctx->getBels()) {
1687 if (ctx->getBelType(bel) != id_GSR)
1688 continue;
1689 ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
1690 ctx->gsrclk_wire = ctx->getBelPinWire(bel, id_CLK);
1691 }
1692 }
1693 }
1694 }
1695
1696 // Preplace PLL
preplace_plls()1697 void preplace_plls()
1698 {
1699 std::set<BelId> available_plls;
1700 for (auto bel : ctx->getBels()) {
1701 if (ctx->getBelType(bel) == id_EHXPLLL && ctx->checkBelAvail(bel))
1702 available_plls.insert(bel);
1703 }
1704 for (auto cell : sorted(ctx->cells)) {
1705 CellInfo *ci = cell.second;
1706 if (ci->type == id_EHXPLLL && ci->attrs.count(ctx->id("BEL")))
1707 available_plls.erase(ctx->getBelByName(ctx->id(ci->attrs.at(ctx->id("BEL")).as_string())));
1708 }
1709 // Place PLL connected to fixed drivers such as IO close to their source
1710 for (auto cell : sorted(ctx->cells)) {
1711 CellInfo *ci = cell.second;
1712 if (ci->type == id_EHXPLLL && !ci->attrs.count(ctx->id("BEL"))) {
1713 const NetInfo *drivernet = net_or_nullptr(ci, id_CLKI);
1714 if (drivernet == nullptr || drivernet->driver.cell == nullptr)
1715 continue;
1716 const CellInfo *drivercell = drivernet->driver.cell;
1717 if (!drivercell->attrs.count(ctx->id("BEL")))
1718 continue;
1719 BelId drvbel = ctx->getBelByName(ctx->id(drivercell->attrs.at(ctx->id("BEL")).as_string()));
1720 Loc drvloc = ctx->getBelLocation(drvbel);
1721 BelId closest_pll;
1722 int closest_distance = std::numeric_limits<int>::max();
1723 for (auto bel : available_plls) {
1724 Loc pllloc = ctx->getBelLocation(bel);
1725 int distance = std::abs(drvloc.x - pllloc.x) + std::abs(drvloc.y - pllloc.y);
1726 if (distance < closest_distance) {
1727 closest_pll = bel;
1728 closest_distance = distance;
1729 }
1730 }
1731 if (closest_pll == BelId())
1732 log_error("failed to place PLL '%s'\n", ci->name.c_str(ctx));
1733 available_plls.erase(closest_pll);
1734 ci->attrs[ctx->id("BEL")] = ctx->getBelName(closest_pll).str(ctx);
1735 }
1736 }
1737 // Place PLLs driven by logic, etc, randomly
1738 for (auto cell : sorted(ctx->cells)) {
1739 CellInfo *ci = cell.second;
1740 if (ci->type == id_EHXPLLL && !ci->attrs.count(ctx->id("BEL"))) {
1741 if (available_plls.empty())
1742 log_error("failed to place PLL '%s'\n", ci->name.c_str(ctx));
1743 BelId next_pll = *(available_plls.begin());
1744 available_plls.erase(next_pll);
1745 ci->attrs[ctx->id("BEL")] = ctx->getBelName(next_pll).str(ctx);
1746 }
1747 }
1748 }
1749
1750 // Check if two nets have identical constant drivers
equal_constant(NetInfo * a,NetInfo * b)1751 bool equal_constant(NetInfo *a, NetInfo *b)
1752 {
1753 if (a->driver.cell == nullptr || b->driver.cell == nullptr)
1754 return (a->driver.cell == nullptr && b->driver.cell == nullptr);
1755 if (a->driver.cell->type != ctx->id("GND") && a->driver.cell->type != ctx->id("VCC"))
1756 return false;
1757 return a->driver.cell->type == b->driver.cell->type;
1758 }
1759
1760 struct EdgeClockInfo
1761 {
1762 CellInfo *buffer = nullptr;
1763 NetInfo *unbuf = nullptr;
1764 NetInfo *buf = nullptr;
1765 };
1766
1767 std::map<std::pair<int, int>, EdgeClockInfo> eclks;
1768 std::map<NetInfo *, int> bridge_side_hint;
1769
make_eclk(PortInfo & usr_port,CellInfo * usr_cell,BelId usr_bel,int bank)1770 void make_eclk(PortInfo &usr_port, CellInfo *usr_cell, BelId usr_bel, int bank)
1771 {
1772 NetInfo *ecknet = usr_port.net;
1773 if (ecknet == nullptr)
1774 log_error("Input '%s' of cell '%s' cannot be disconnected\n", usr_port.name.c_str(ctx),
1775 usr_cell->name.c_str(ctx));
1776 int found_eclk = -1, free_eclk = -1;
1777 for (int i = 0; i < 2; i++) {
1778 if (eclks.count(std::make_pair(bank, i))) {
1779 if (eclks.at(std::make_pair(bank, i)).unbuf == ecknet) {
1780 found_eclk = i;
1781 break;
1782 }
1783 } else if (free_eclk == -1) {
1784 if (bridge_side_hint.count(ecknet) && bridge_side_hint.at(ecknet) != i)
1785 continue;
1786 free_eclk = i;
1787 }
1788 }
1789 if (found_eclk == -1) {
1790 if (free_eclk == -1) {
1791 log_error("Unable to promote edge clock '%s' for bank %d. 2/2 edge clocks already used by '%s' and "
1792 "'%s'.\n",
1793 ecknet->name.c_str(ctx), bank, eclks.at(std::make_pair(bank, 0)).unbuf->name.c_str(ctx),
1794 eclks.at(std::make_pair(bank, 1)).unbuf->name.c_str(ctx));
1795 } else {
1796 log_info("Promoted '%s' to bank %d ECLK%d.\n", ecknet->name.c_str(ctx), bank, free_eclk);
1797 auto &eclk = eclks[std::make_pair(bank, free_eclk)];
1798 eclk.unbuf = ecknet;
1799 IdString eckname = ctx->id(ecknet->name.str(ctx) + "$eclk" + std::to_string(bank) + "_" +
1800 std::to_string(free_eclk));
1801
1802 std::unique_ptr<NetInfo> promoted_ecknet(new NetInfo);
1803 promoted_ecknet->name = eckname;
1804 promoted_ecknet->attrs[ctx->id("ECP5_IS_GLOBAL")] = 1; // Prevents router etc touching this special net
1805 eclk.buf = promoted_ecknet.get();
1806 NPNR_ASSERT(!ctx->nets.count(eckname));
1807 ctx->nets[eckname] = std::move(promoted_ecknet);
1808
1809 // Insert TRELLIS_ECLKBUF to isolate edge clock from general routing
1810 std::unique_ptr<CellInfo> eclkbuf =
1811 create_ecp5_cell(ctx, id_TRELLIS_ECLKBUF, eckname.str(ctx) + "$buffer");
1812 BelId target_bel;
1813 // Find the correct Bel for the ECLKBUF
1814 IdString eclkname = ctx->id("G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(free_eclk));
1815 for (auto bel : ctx->getBels()) {
1816 if (ctx->getBelType(bel) != id_TRELLIS_ECLKBUF)
1817 continue;
1818 if (ctx->getWireBasename(ctx->getBelPinWire(bel, id_ECLKO)) != eclkname)
1819 continue;
1820 target_bel = bel;
1821 break;
1822 }
1823 NPNR_ASSERT(target_bel != BelId());
1824
1825 eclkbuf->attrs[ctx->id("BEL")] = ctx->getBelName(target_bel).str(ctx);
1826
1827 connect_port(ctx, ecknet, eclkbuf.get(), id_ECLKI);
1828 connect_port(ctx, eclk.buf, eclkbuf.get(), id_ECLKO);
1829 found_eclk = free_eclk;
1830 eclk.buffer = eclkbuf.get();
1831 new_cells.push_back(std::move(eclkbuf));
1832 }
1833 }
1834
1835 auto &eclk = eclks[std::make_pair(bank, found_eclk)];
1836 disconnect_port(ctx, usr_cell, usr_port.name);
1837 usr_port.net = nullptr;
1838 connect_port(ctx, eclk.buf, usr_cell, usr_port.name);
1839
1840 // Simple ECLK router
1841 WireId userWire = ctx->getBelPinWire(usr_bel, usr_port.name);
1842 IdString bnke_name = ctx->id("BNK_ECLK" + std::to_string(found_eclk));
1843 IdString global_name = ctx->id("G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(found_eclk));
1844
1845 std::queue<WireId> upstream;
1846 std::unordered_map<WireId, PipId> backtrace;
1847 upstream.push(userWire);
1848 WireId next;
1849 while (true) {
1850 if (upstream.empty() || upstream.size() > 30000)
1851 log_error("failed to route bank %d ECLK%d to %s.%s\n", bank, found_eclk,
1852 ctx->getBelName(usr_bel).c_str(ctx), usr_port.name.c_str(ctx));
1853 next = upstream.front();
1854 upstream.pop();
1855 if (ctx->debug)
1856 log_info(" visited %s\n", ctx->getWireName(next).c_str(ctx));
1857 IdString basename = ctx->getWireBasename(next);
1858 if (basename == bnke_name || basename == global_name) {
1859 break;
1860 }
1861 if (ctx->checkWireAvail(next)) {
1862 for (auto pip : ctx->getPipsUphill(next)) {
1863 WireId src = ctx->getPipSrcWire(pip);
1864 backtrace[src] = pip;
1865 upstream.push(src);
1866 }
1867 }
1868 }
1869 // Set all the pips we found along the way
1870 WireId cursor = next;
1871 while (true) {
1872 auto fnd = backtrace.find(cursor);
1873 if (fnd == backtrace.end())
1874 break;
1875 ctx->bindPip(fnd->second, eclk.buf, STRENGTH_LOCKED);
1876 cursor = ctx->getPipDstWire(fnd->second);
1877 }
1878 }
1879
tie_zero(CellInfo * ci,IdString port)1880 void tie_zero(CellInfo *ci, IdString port)
1881 {
1882
1883 if (!ci->ports.count(port)) {
1884 ci->ports[port].name = port;
1885 ci->ports[port].type = PORT_IN;
1886 }
1887
1888 std::unique_ptr<CellInfo> zero_cell{new CellInfo};
1889 std::unique_ptr<NetInfo> zero_net{new NetInfo};
1890 IdString name = ctx->id(ci->name.str(ctx) + "$zero$" + port.str(ctx));
1891 zero_cell->type = ctx->id("GND");
1892 zero_cell->name = name;
1893 zero_net->name = name;
1894 zero_cell->ports[ctx->id("GND")].type = PORT_OUT;
1895 connect_port(ctx, zero_net.get(), zero_cell.get(), ctx->id("GND"));
1896 connect_port(ctx, zero_net.get(), ci, port);
1897 ctx->nets[name] = std::move(zero_net);
1898 new_cells.push_back(std::move(zero_cell));
1899 }
1900
1901 std::unordered_map<IdString, std::pair<bool, int>> dqsbuf_dqsg;
1902 // Pack DQSBUFs
pack_dqsbuf()1903 void pack_dqsbuf()
1904 {
1905 for (auto cell : sorted(ctx->cells)) {
1906 CellInfo *ci = cell.second;
1907 if (ci->type == id_DQSBUFM) {
1908 CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("DQSI")).net, is_trellis_io, id_O);
1909 if (pio == nullptr || ci->ports.at(ctx->id("DQSI")).net->users.size() > 1)
1910 log_error("DQSBUFM '%s' DQSI input must be connected only to a top level input\n",
1911 ci->name.c_str(ctx));
1912 if (!pio->attrs.count(ctx->id("BEL")))
1913 log_error("DQSBUFM can only be used with a pin-constrained PIO connected to its DQSI input"
1914 "(while processing '%s').\n",
1915 ci->name.c_str(ctx));
1916 BelId pio_bel = ctx->getBelByName(ctx->id(pio->attrs.at(ctx->id("BEL")).as_string()));
1917 NPNR_ASSERT(pio_bel != BelId());
1918 Loc pio_loc = ctx->getBelLocation(pio_bel);
1919 if (pio_loc.z != 0)
1920 log_error("PIO '%s' does not appear to be a DQS site (expecting an 'A' pin).\n",
1921 ctx->getBelName(pio_bel).c_str(ctx));
1922 pio_loc.z = 8;
1923 BelId dqsbuf = ctx->getBelByLocation(pio_loc);
1924 if (dqsbuf == BelId() || ctx->getBelType(dqsbuf) != id_DQSBUFM)
1925 log_error("PIO '%s' does not appear to be a DQS site (didn't find a DQSBUFM).\n",
1926 ctx->getBelName(pio_bel).c_str(ctx));
1927 ci->attrs[ctx->id("BEL")] = ctx->getBelName(dqsbuf).str(ctx);
1928 bool got_dqsg = ctx->getPIODQSGroup(pio_bel, dqsbuf_dqsg[ci->name].first, dqsbuf_dqsg[ci->name].second);
1929 NPNR_ASSERT(got_dqsg);
1930 log_info("Constrained DQSBUFM '%s' to %cDQS%d\n", ci->name.c_str(ctx),
1931 dqsbuf_dqsg[ci->name].first ? 'R' : 'L', dqsbuf_dqsg[ci->name].second);
1932
1933 // Set all special ports, if used as 'globals' that the router won't touch
1934 for (auto port : {id_DQSR90, id_RDPNTR0, id_RDPNTR1, id_RDPNTR2, id_WRPNTR0, id_WRPNTR1, id_WRPNTR2,
1935 id_DQSW270, id_DQSW}) {
1936 if (!ci->ports.count(port))
1937 continue;
1938 NetInfo *pn = ci->ports.at(port).net;
1939 if (pn == nullptr)
1940 continue;
1941 for (auto &usr : pn->users) {
1942 if (usr.port != port ||
1943 (usr.cell->type != ctx->id("ODDRX2DQA") && usr.cell->type != ctx->id("ODDRX2DQSB") &&
1944 usr.cell->type != ctx->id("TSHX2DQSA") && usr.cell->type != ctx->id("IDDRX2DQA") &&
1945 usr.cell->type != ctx->id("TSHX2DQA") && usr.cell->type != id_IOLOGIC))
1946 log_error("Port '%s' of DQSBUFM '%s' cannot drive port '%s' of cell '%s'.\n",
1947 port.c_str(ctx), ci->name.c_str(ctx), usr.port.c_str(ctx),
1948 usr.cell->name.c_str(ctx));
1949 }
1950 pn->attrs[ctx->id("ECP5_IS_GLOBAL")] = 1;
1951 }
1952
1953 for (auto zport :
1954 {id_RDMOVE, id_RDDIRECTION, id_WRMOVE, id_WRDIRECTION, id_READ0, id_READ1, id_READCLKSEL0,
1955 id_READCLKSEL1, id_READCLKSEL2, id_DYNDELAY0, id_DYNDELAY1, id_DYNDELAY2, id_DYNDELAY3,
1956 id_DYNDELAY4, id_DYNDELAY5, id_DYNDELAY6, id_DYNDELAY7}) {
1957 if (net_or_nullptr(ci, zport) == nullptr)
1958 tie_zero(ci, zport);
1959 }
1960 }
1961 }
1962 }
1963
lookup_delay(const std::string & del_mode)1964 int lookup_delay(const std::string &del_mode)
1965 {
1966 if (del_mode == "USER_DEFINED")
1967 return 0;
1968 else if (del_mode == "DQS_ALIGNED_X2")
1969 return 6;
1970 else if (del_mode == "DQS_CMD_CLK")
1971 return 9;
1972 else if (del_mode == "ECLK_ALIGNED")
1973 return 21;
1974 else if (del_mode == "ECLK_CENTERED")
1975 return 11;
1976 else if (del_mode == "ECLKBRIDGE_ALIGNED")
1977 return 39;
1978 else if (del_mode == "ECLKBRIDGE_CENTERED")
1979 return 29;
1980 else if (del_mode == "SCLK_ALIGNED")
1981 return 50;
1982 else if (del_mode == "SCLK_CENTERED")
1983 return 39;
1984 else if (del_mode == "SCLK_ZEROHOLD")
1985 return 59;
1986 else
1987 log_error("Unsupported DEL_MODE '%s'\n", del_mode.c_str());
1988 }
1989
1990 // Pack IOLOGIC
pack_iologic()1991 void pack_iologic()
1992 {
1993 std::unordered_map<IdString, CellInfo *> pio_iologic;
1994
1995 auto set_iologic_sclk = [&](CellInfo *iol, CellInfo *prim, IdString port, bool input, bool disconnect = true) {
1996 NetInfo *sclk = nullptr;
1997 if (prim->ports.count(port))
1998 sclk = prim->ports[port].net;
1999 if (sclk == nullptr) {
2000 iol->params[input ? ctx->id("CLKIMUX") : ctx->id("CLKOMUX")] = std::string("0");
2001 } else {
2002 iol->params[input ? ctx->id("CLKIMUX") : ctx->id("CLKOMUX")] = std::string("CLK");
2003 if (iol->ports[id_CLK].net != nullptr) {
2004 if (iol->ports[id_CLK].net != sclk && !equal_constant(iol->ports[id_CLK].net, sclk))
2005 log_error("IOLOGIC '%s' has conflicting clocks '%s' and '%s'\n", iol->name.c_str(ctx),
2006 iol->ports[id_CLK].net->name.c_str(ctx), sclk->name.c_str(ctx));
2007 } else {
2008 connect_port(ctx, sclk, iol, id_CLK);
2009 }
2010 }
2011 if (prim->ports.count(port) && disconnect)
2012 disconnect_port(ctx, prim, port);
2013 };
2014
2015 auto set_iologic_eclk = [&](CellInfo *iol, CellInfo *prim, IdString port) {
2016 NetInfo *eclk = nullptr;
2017 if (prim->ports.count(port))
2018 eclk = prim->ports[port].net;
2019 if (eclk == nullptr)
2020 log_error("%s '%s' cannot have disconnected ECLK", prim->type.c_str(ctx), prim->name.c_str(ctx));
2021
2022 if (iol->ports[id_ECLK].net != nullptr) {
2023 if (iol->ports[id_ECLK].net != eclk)
2024 log_error("IOLOGIC '%s' has conflicting ECLKs '%s' and '%s'\n", iol->name.c_str(ctx),
2025 iol->ports[id_ECLK].net->name.c_str(ctx), eclk->name.c_str(ctx));
2026 } else {
2027 connect_port(ctx, eclk, iol, id_ECLK);
2028 }
2029 if (prim->ports.count(port))
2030 disconnect_port(ctx, prim, port);
2031 };
2032
2033 auto set_iologic_lsr = [&](CellInfo *iol, CellInfo *prim, IdString port, bool input, bool disconnect = true) {
2034 NetInfo *lsr = nullptr;
2035 if (prim->ports.count(port))
2036 lsr = prim->ports[port].net;
2037 if (lsr == nullptr) {
2038 iol->params[input ? ctx->id("LSRIMUX") : ctx->id("LSROMUX")] = std::string("0");
2039 } else {
2040 iol->params[input ? ctx->id("LSRIMUX") : ctx->id("LSROMUX")] = std::string("LSRMUX");
2041 if (iol->ports[id_LSR].net != nullptr && !equal_constant(iol->ports[id_LSR].net, lsr)) {
2042 if (iol->ports[id_LSR].net != lsr)
2043 log_error("IOLOGIC '%s' has conflicting LSR signals '%s' and '%s'\n", iol->name.c_str(ctx),
2044 iol->ports[id_LSR].net->name.c_str(ctx), lsr->name.c_str(ctx));
2045 } else if (iol->ports[id_LSR].net == nullptr) {
2046 connect_port(ctx, lsr, iol, id_LSR);
2047 }
2048 }
2049 if (prim->ports.count(port) && disconnect)
2050 disconnect_port(ctx, prim, port);
2051 };
2052
2053 bool warned_oddrx_iddrx = false;
2054
2055 auto set_iologic_mode = [&](CellInfo *iol, std::string mode) {
2056 auto &curr_mode = iol->params[ctx->id("MODE")].str;
2057 if (curr_mode != "NONE" && mode == "IREG_OREG")
2058 return;
2059 if ((curr_mode == "IDDRXN" && mode == "ODDRXN") || (curr_mode == "ODDRXN" && mode == "IDDRXN")) {
2060 if (!warned_oddrx_iddrx) {
2061 warned_oddrx_iddrx = true;
2062 log_warning("Use of IDDRXN and ODDRXN primitives on the same pin is unofficial and unsupported!\n");
2063 }
2064 curr_mode = "ODDRXN";
2065 return;
2066 }
2067 if (curr_mode != "NONE" && curr_mode != "IREG_OREG" && curr_mode != mode)
2068 log_error("IOLOGIC '%s' has conflicting modes '%s' and '%s'\n", iol->name.c_str(ctx), curr_mode.c_str(),
2069 mode.c_str());
2070 if (iol->type == id_SIOLOGIC && mode != "IREG_OREG" && mode != "IDDRX1_ODDRX1" && mode != "NONE")
2071 log_error("IOLOGIC '%s' is set to mode '%s', but this is only supported for left and right IO\n",
2072 iol->name.c_str(ctx), mode.c_str());
2073 curr_mode = mode;
2074 };
2075
2076 auto get_pio_bel = [&](CellInfo *pio, CellInfo *curr) {
2077 if (!pio->attrs.count(ctx->id("BEL")))
2078 log_error("IOLOGIC functionality (DDR, DELAY, DQS, etc) can only be used with pin-constrained PIO "
2079 "(while processing '%s').\n",
2080 curr->name.c_str(ctx));
2081 BelId bel = ctx->getBelByName(ctx->id(pio->attrs.at(ctx->id("BEL")).as_string()));
2082 NPNR_ASSERT(bel != BelId());
2083 return bel;
2084 };
2085
2086 auto create_pio_iologic = [&](CellInfo *pio, CellInfo *curr) {
2087 BelId bel = get_pio_bel(pio, curr);
2088 log_info("IOLOGIC component %s connected to PIO Bel %s\n", curr->name.c_str(ctx),
2089 ctx->getBelName(bel).c_str(ctx));
2090 Loc loc = ctx->getBelLocation(bel);
2091 bool s = false;
2092 if (loc.y == 0 || loc.y == (ctx->chip_info->height - 1))
2093 s = true;
2094 std::unique_ptr<CellInfo> iol =
2095 create_ecp5_cell(ctx, s ? id_SIOLOGIC : id_IOLOGIC, pio->name.str(ctx) + "$IOL");
2096
2097 loc.z += s ? 2 : 4;
2098 iol->attrs[ctx->id("BEL")] = ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx);
2099
2100 CellInfo *iol_ptr = iol.get();
2101 pio_iologic[pio->name] = iol_ptr;
2102 new_cells.push_back(std::move(iol));
2103 return iol_ptr;
2104 };
2105
2106 auto process_dqs_port = [&](CellInfo *prim, CellInfo *pio, CellInfo *iol, IdString port) {
2107 NetInfo *sig = nullptr;
2108 if (prim->ports.count(port))
2109 sig = prim->ports[port].net;
2110 if (sig == nullptr || sig->driver.cell == nullptr)
2111 log_error("Port %s of cell '%s' cannot be disconnected, it must be driven by a DQSBUFM\n",
2112 port.c_str(ctx), prim->name.c_str(ctx));
2113 if (iol->ports.at(port).net != nullptr) {
2114 if (iol->ports.at(port).net != sig) {
2115 log_error("IOLOGIC '%s' has conflicting %s signals '%s' and '%s'\n", iol->name.c_str(ctx),
2116 port.c_str(ctx), iol->ports[port].net->name.c_str(ctx), sig->name.c_str(ctx));
2117 }
2118 disconnect_port(ctx, prim, port);
2119 } else {
2120 bool dqsr;
2121 int dqsgroup;
2122 bool has_dqs = ctx->getPIODQSGroup(get_pio_bel(pio, prim), dqsr, dqsgroup);
2123 if (!has_dqs)
2124 log_error("Primitive '%s' cannot be connected to top level port '%s' as the associated pin is not "
2125 "in any DQS group",
2126 prim->name.c_str(ctx), pio->name.c_str(ctx));
2127 if (sig->driver.cell->type != id_DQSBUFM || sig->driver.port != port)
2128 log_error("Port %s of cell '%s' must be driven by port %s of a DQSBUFM", port.c_str(ctx),
2129 prim->name.c_str(ctx), port.c_str(ctx));
2130 auto &driver_group = dqsbuf_dqsg.at(sig->driver.cell->name);
2131 if (driver_group.first != dqsr || driver_group.second != dqsgroup)
2132 log_error("DQS group mismatch, port %s of '%s' in group %cDQ%d is driven by DQSBUFM '%s' in group "
2133 "%cDQ%d\n",
2134 port.c_str(ctx), prim->name.c_str(ctx), dqsr ? 'R' : 'L', dqsgroup,
2135 sig->driver.cell->name.c_str(ctx), driver_group.first ? 'R' : 'L', driver_group.second);
2136 replace_port(prim, port, iol, port);
2137 }
2138 };
2139
2140 for (auto cell : sorted(ctx->cells)) {
2141 CellInfo *ci = cell.second;
2142 if (ci->type == ctx->id("DELAYF") || ci->type == ctx->id("DELAYG")) {
2143 CellInfo *i_pio = net_driven_by(ctx, ci->ports.at(ctx->id("A")).net, is_trellis_io, id_O);
2144 CellInfo *o_pio = net_only_drives(ctx, ci->ports.at(ctx->id("Z")).net, is_trellis_io, id_I, true);
2145 CellInfo *iol = nullptr;
2146 if (i_pio != nullptr && ci->ports.at(ctx->id("A")).net->users.size() == 1) {
2147 iol = create_pio_iologic(i_pio, ci);
2148 set_iologic_mode(iol, "IREG_OREG");
2149 bool drives_iologic = false;
2150 for (auto user : ci->ports.at(ctx->id("Z")).net->users)
2151 if (is_iologic_input_cell(ctx, user.cell) && user.port == ctx->id("D"))
2152 drives_iologic = true;
2153 if (drives_iologic) {
2154 // Reconnect to PIO which the packer expects later on
2155 NetInfo *input_net = ci->ports.at(ctx->id("A")).net, *dly_net = ci->ports.at(ctx->id("Z")).net;
2156 disconnect_port(ctx, i_pio, id_O);
2157 i_pio->ports.at(id_O).net = nullptr;
2158 disconnect_port(ctx, ci, id_A);
2159 ci->ports.at(id_A).net = nullptr;
2160 disconnect_port(ctx, ci, id_Z);
2161 ci->ports.at(id_Z).net = nullptr;
2162 connect_port(ctx, dly_net, i_pio, id_O);
2163 connect_port(ctx, input_net, iol, id_INDD);
2164 connect_port(ctx, input_net, iol, id_DI);
2165 } else {
2166 replace_port(ci, id_A, iol, id_PADDI);
2167 replace_port(ci, id_Z, iol, id_INDD);
2168 }
2169 packed_cells.insert(cell.first);
2170 } else if (o_pio != nullptr) {
2171 iol = create_pio_iologic(o_pio, ci);
2172 iol->params[ctx->id("DELAY.OUTDEL")] = std::string("ENABLED");
2173 bool driven_by_iol = false;
2174 NetInfo *input_net = ci->ports.at(ctx->id("A")).net, *dly_net = ci->ports.at(ctx->id("Z")).net;
2175 if (input_net->driver.cell != nullptr && is_iologic_output_cell(ctx, input_net->driver.cell) &&
2176 input_net->driver.port == ctx->id("Q"))
2177 driven_by_iol = true;
2178 if (driven_by_iol) {
2179 disconnect_port(ctx, o_pio, id_I);
2180 o_pio->ports.at(id_I).net = nullptr;
2181 disconnect_port(ctx, ci, id_A);
2182 ci->ports.at(id_A).net = nullptr;
2183 disconnect_port(ctx, ci, id_Z);
2184 ci->ports.at(id_Z).net = nullptr;
2185 connect_port(ctx, input_net, o_pio, id_I);
2186 ctx->nets.erase(dly_net->name);
2187 } else {
2188 replace_port(ci, ctx->id("A"), iol, id_TXDATA0);
2189 replace_port(ci, ctx->id("Z"), iol, id_IOLDO);
2190 if (!o_pio->ports.count(id_IOLDO)) {
2191 o_pio->ports[id_IOLDO].name = id_IOLDO;
2192 o_pio->ports[id_IOLDO].type = PORT_IN;
2193 }
2194 replace_port(o_pio, id_I, o_pio, id_IOLDO);
2195 }
2196 packed_cells.insert(cell.first);
2197 } else {
2198 log_error("%s '%s' must be connected directly to top level input or output\n", ci->type.c_str(ctx),
2199 ci->name.c_str(ctx));
2200 }
2201 iol->params[ctx->id("DELAY.DEL_VALUE")] =
2202 lookup_delay(str_or_default(ci->params, ctx->id("DEL_MODE"), "USER_DEFINED"));
2203 if (ci->params.count(ctx->id("DEL_VALUE")) &&
2204 (!ci->params.at(ctx->id("DEL_VALUE")).is_string ||
2205 std::string(ci->params.at(ctx->id("DEL_VALUE")).as_string()).substr(0, 5) != "DELAY"))
2206 iol->params[ctx->id("DELAY.DEL_VALUE")] = ci->params.at(ctx->id("DEL_VALUE"));
2207 if (ci->ports.count(id_LOADN))
2208 replace_port(ci, id_LOADN, iol, id_LOADN);
2209 else
2210 tie_zero(iol, id_LOADN);
2211 if (ci->ports.count(id_MOVE))
2212 replace_port(ci, id_MOVE, iol, id_MOVE);
2213 else
2214 tie_zero(iol, id_MOVE);
2215 if (ci->ports.count(id_DIRECTION))
2216 replace_port(ci, id_DIRECTION, iol, id_DIRECTION);
2217 else
2218 tie_zero(iol, id_DIRECTION);
2219 if (ci->ports.count(id_CFLAG))
2220 replace_port(ci, id_CFLAG, iol, id_CFLAG);
2221 }
2222 }
2223
2224 for (auto cell : sorted(ctx->cells)) {
2225 CellInfo *ci = cell.second;
2226 if (ci->type == ctx->id("IDDRX1F")) {
2227 CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
2228 if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
2229 log_error("IDDRX1F '%s' D input must be connected only to a top level input\n",
2230 ci->name.c_str(ctx));
2231 CellInfo *iol;
2232 if (pio_iologic.count(pio->name))
2233 iol = pio_iologic.at(pio->name);
2234 else
2235 iol = create_pio_iologic(pio, ci);
2236 set_iologic_mode(iol, "IDDRX1_ODDRX1");
2237 replace_port(ci, ctx->id("D"), iol, id_PADDI);
2238 set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
2239 set_iologic_lsr(iol, ci, ctx->id("RST"), true);
2240 replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
2241 replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
2242 iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
2243 packed_cells.insert(cell.first);
2244 } else if (ci->type == ctx->id("ODDRX1F")) {
2245 CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
2246 if (pio == nullptr)
2247 log_error("ODDRX1F '%s' Q output must be connected only to a top level output\n",
2248 ci->name.c_str(ctx));
2249 CellInfo *iol;
2250 if (pio_iologic.count(pio->name))
2251 iol = pio_iologic.at(pio->name);
2252 else
2253 iol = create_pio_iologic(pio, ci);
2254 set_iologic_mode(iol, "IDDRX1_ODDRX1");
2255 replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
2256 if (!pio->ports.count(id_IOLDO)) {
2257 pio->ports[id_IOLDO].name = id_IOLDO;
2258 pio->ports[id_IOLDO].type = PORT_IN;
2259 }
2260 replace_port(pio, id_I, pio, id_IOLDO);
2261 pio->params[ctx->id("DATAMUX_ODDR")] = std::string("IOLDO");
2262 set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
2263 set_iologic_lsr(iol, ci, ctx->id("RST"), false);
2264 replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
2265 replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
2266 iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
2267 packed_cells.insert(cell.first);
2268 } else if (ci->type == ctx->id("ODDRX2F") || ci->type == ctx->id("ODDR71B")) {
2269 CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
2270 if (pio == nullptr)
2271 log_error("%s '%s' Q output must be connected only to a top level output\n", ci->type.c_str(ctx),
2272 ci->name.c_str(ctx));
2273 CellInfo *iol;
2274 if (pio_iologic.count(pio->name))
2275 iol = pio_iologic.at(pio->name);
2276 else
2277 iol = create_pio_iologic(pio, ci);
2278 set_iologic_mode(iol, "ODDRXN");
2279 replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
2280 if (!pio->ports.count(id_IOLDO)) {
2281 pio->ports[id_IOLDO].name = id_IOLDO;
2282 pio->ports[id_IOLDO].type = PORT_IN;
2283 }
2284 replace_port(pio, id_I, pio, id_IOLDO);
2285 set_iologic_sclk(iol, ci, ctx->id("SCLK"), false, false);
2286 set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
2287 set_iologic_eclk(iol, ci, id_ECLK);
2288 set_iologic_lsr(iol, ci, ctx->id("RST"), false, false);
2289 set_iologic_lsr(iol, ci, ctx->id("RST"), true);
2290 replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
2291 replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
2292 replace_port(ci, ctx->id("D2"), iol, id_TXDATA2);
2293 replace_port(ci, ctx->id("D3"), iol, id_TXDATA3);
2294 if (ci->type == ctx->id("ODDR71B")) {
2295 Loc loc =
2296 ctx->getBelLocation(ctx->getBelByName(ctx->id(pio->attrs.at(ctx->id("BEL")).as_string())));
2297 if (loc.z % 2 == 1)
2298 log_error("ODDR71B '%s' can only be used at 'A' or 'C' locations\n", ci->name.c_str(ctx));
2299 replace_port(ci, ctx->id("D4"), iol, id_TXDATA4);
2300 replace_port(ci, ctx->id("D5"), iol, id_TXDATA5);
2301 replace_port(ci, ctx->id("D6"), iol, id_TXDATA6);
2302 iol->params[ctx->id("ODDRXN.MODE")] = std::string("ODDR71");
2303 } else {
2304 iol->params[ctx->id("ODDRXN.MODE")] = std::string("ODDRX2");
2305 }
2306 iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
2307 pio->params[ctx->id("DATAMUX_ODDR")] = std::string("IOLDO");
2308 packed_cells.insert(cell.first);
2309 } else if (ci->type == ctx->id("IDDRX2F") || ci->type == ctx->id("IDDR71B")) {
2310 CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
2311 if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
2312 log_error("%s '%s' D input must be connected only to a top level input\n", ci->type.c_str(ctx),
2313 ci->name.c_str(ctx));
2314 CellInfo *iol;
2315 if (pio_iologic.count(pio->name))
2316 iol = pio_iologic.at(pio->name);
2317 else
2318 iol = create_pio_iologic(pio, ci);
2319 set_iologic_mode(iol, "IDDRXN");
2320 replace_port(ci, ctx->id("D"), iol, id_PADDI);
2321 set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
2322 set_iologic_eclk(iol, ci, id_ECLK);
2323 set_iologic_lsr(iol, ci, ctx->id("RST"), true);
2324 replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
2325 replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
2326 replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2);
2327 replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3);
2328 if (ci->type == ctx->id("IDDR71B")) {
2329 Loc loc =
2330 ctx->getBelLocation(ctx->getBelByName(ctx->id(pio->attrs.at(ctx->id("BEL")).as_string())));
2331 if (loc.z % 2 == 1)
2332 log_error("IDDR71B '%s' can only be used at 'A' or 'C' locations\n", ci->name.c_str(ctx));
2333 replace_port(ci, ctx->id("Q4"), iol, id_RXDATA4);
2334 replace_port(ci, ctx->id("Q5"), iol, id_RXDATA5);
2335 replace_port(ci, ctx->id("Q6"), iol, id_RXDATA6);
2336 replace_port(ci, ctx->id("ALIGNWD"), iol, id_SLIP);
2337 iol->params[ctx->id("IDDRXN.MODE")] = std::string("IDDR71");
2338 } else {
2339 iol->params[ctx->id("IDDRXN.MODE")] = std::string("IDDRX2");
2340 }
2341 iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
2342 packed_cells.insert(cell.first);
2343 } else if (ci->type == ctx->id("OSHX2A")) {
2344 CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
2345 if (pio == nullptr)
2346 log_error("OSHX2A '%s' Q output must be connected only to a top level output\n",
2347 ci->name.c_str(ctx));
2348 CellInfo *iol;
2349 if (pio_iologic.count(pio->name))
2350 iol = pio_iologic.at(pio->name);
2351 else
2352 iol = create_pio_iologic(pio, ci);
2353 set_iologic_mode(iol, "MIDDRX_MODDRX");
2354 replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
2355 if (!pio->ports.count(id_IOLDO)) {
2356 pio->ports[id_IOLDO].name = id_IOLDO;
2357 pio->ports[id_IOLDO].type = PORT_IN;
2358 }
2359 replace_port(pio, id_I, pio, id_IOLDO);
2360 set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
2361 set_iologic_eclk(iol, ci, id_ECLK);
2362 set_iologic_lsr(iol, ci, ctx->id("RST"), false, false);
2363 set_iologic_lsr(iol, ci, ctx->id("RST"), true);
2364 replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
2365 replace_port(ci, ctx->id("D1"), iol, id_TXDATA2);
2366 iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
2367 iol->params[ctx->id("MODDRX.MODE")] = std::string("MOSHX2");
2368 pio->params[ctx->id("DATAMUX_MDDR")] = std::string("IOLDO");
2369 packed_cells.insert(cell.first);
2370 } else if (ci->type == ctx->id("ODDRX2DQA") || ci->type == ctx->id("ODDRX2DQSB")) {
2371 CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
2372 if (pio == nullptr)
2373 log_error("%s '%s' Q output must be connected only to a top level output\n", ci->type.c_str(ctx),
2374 ci->name.c_str(ctx));
2375 CellInfo *iol;
2376 if (pio_iologic.count(pio->name))
2377 iol = pio_iologic.at(pio->name);
2378 else
2379 iol = create_pio_iologic(pio, ci);
2380 set_iologic_mode(iol, "MIDDRX_MODDRX");
2381 replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
2382 if (!pio->ports.count(id_IOLDO)) {
2383 pio->ports[id_IOLDO].name = id_IOLDO;
2384 pio->ports[id_IOLDO].type = PORT_IN;
2385 }
2386 replace_port(pio, id_I, pio, id_IOLDO);
2387 set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
2388 set_iologic_eclk(iol, ci, id_ECLK);
2389 set_iologic_lsr(iol, ci, ctx->id("RST"), false, false);
2390 set_iologic_lsr(iol, ci, ctx->id("RST"), true);
2391 replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
2392 replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
2393 replace_port(ci, ctx->id("D2"), iol, id_TXDATA2);
2394 replace_port(ci, ctx->id("D3"), iol, id_TXDATA3);
2395 iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
2396 iol->params[ctx->id("MODDRX.MODE")] = std::string("MODDRX2");
2397 iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] =
2398 std::string(ci->type == ctx->id("ODDRX2DQSB") ? "DQSW" : "DQSW270");
2399 process_dqs_port(ci, pio, iol, ci->type == ctx->id("ODDRX2DQSB") ? id_DQSW : id_DQSW270);
2400 pio->params[ctx->id("DATAMUX_MDDR")] = std::string("IOLDO");
2401 packed_cells.insert(cell.first);
2402 } else if (ci->type == ctx->id("IDDRX2DQA")) {
2403 CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
2404 if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
2405 log_error("IDDRX2DQA '%s' D input must be connected only to a top level input\n",
2406 ci->name.c_str(ctx));
2407 CellInfo *iol;
2408 if (pio_iologic.count(pio->name))
2409 iol = pio_iologic.at(pio->name);
2410 else
2411 iol = create_pio_iologic(pio, ci);
2412 set_iologic_mode(iol, "MIDDRX_MODDRX");
2413 replace_port(ci, ctx->id("D"), iol, id_PADDI);
2414 set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
2415 set_iologic_eclk(iol, ci, id_ECLK);
2416 set_iologic_lsr(iol, ci, ctx->id("RST"), true);
2417 replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
2418 replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
2419 replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2);
2420 replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3);
2421 replace_port(ci, ctx->id("QWL"), iol, id_INFF);
2422 iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
2423 iol->params[ctx->id("MIDDRX.MODE")] = std::string("MIDDRX2");
2424 process_dqs_port(ci, pio, iol, id_DQSR90);
2425 process_dqs_port(ci, pio, iol, id_RDPNTR2);
2426 process_dqs_port(ci, pio, iol, id_RDPNTR1);
2427 process_dqs_port(ci, pio, iol, id_RDPNTR0);
2428 process_dqs_port(ci, pio, iol, id_WRPNTR2);
2429 process_dqs_port(ci, pio, iol, id_WRPNTR1);
2430 process_dqs_port(ci, pio, iol, id_WRPNTR0);
2431 packed_cells.insert(cell.first);
2432 } else if (ci->type == ctx->id("TSHX2DQA") || ci->type == ctx->id("TSHX2DQSA")) {
2433 CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_T, true);
2434 if (pio == nullptr)
2435 log_error("%s '%s' Q output must be connected only to a top level tristate\n", ci->type.c_str(ctx),
2436 ci->name.c_str(ctx));
2437 CellInfo *iol;
2438 if (pio_iologic.count(pio->name))
2439 iol = pio_iologic.at(pio->name);
2440 else
2441 iol = create_pio_iologic(pio, ci);
2442 set_iologic_mode(iol, "MIDDRX_MODDRX");
2443 replace_port(ci, ctx->id("Q"), iol, id_IOLTO);
2444 if (!pio->ports.count(id_IOLTO)) {
2445 pio->ports[id_IOLTO].name = id_IOLTO;
2446 pio->ports[id_IOLTO].type = PORT_IN;
2447 }
2448 replace_port(pio, id_T, pio, id_IOLTO);
2449 set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
2450 set_iologic_eclk(iol, ci, id_ECLK);
2451 set_iologic_lsr(iol, ci, ctx->id("RST"), false);
2452 replace_port(ci, ctx->id("T0"), iol, id_TSDATA0);
2453 replace_port(ci, ctx->id("T1"), iol, id_TSDATA1);
2454 process_dqs_port(ci, pio, iol, ci->type == ctx->id("TSHX2DQSA") ? id_DQSW : id_DQSW270);
2455 iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
2456 iol->params[ctx->id("MTDDRX.MODE")] = std::string("MTSHX2");
2457 iol->params[ctx->id("MTDDRX.REGSET")] = std::string("SET");
2458 iol->params[ctx->id("MTDDRX.DQSW_INVERT")] =
2459 std::string(ci->type == ctx->id("TSHX2DQSA") ? "ENABLED" : "DISABLED");
2460 iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] =
2461 std::string(ci->type == ctx->id("TSHX2DQSA") ? "DQSW" : "DQSW270");
2462 iol->params[ctx->id("IOLTOMUX")] = std::string("TDDR");
2463 packed_cells.insert(cell.first);
2464 } else if (ci->type == ctx->id("TRELLIS_FF") && bool_or_default(ci->attrs, ctx->id("syn_useioff"))) {
2465 // Pack IO flipflop into IOLOGIC
2466 std::string mode = str_or_default(ci->attrs, ctx->id("ioff_dir"), "");
2467 if (mode != "output") {
2468 // See if it can be packed as an input ff
2469 NetInfo *d = get_net_or_empty(ci, ctx->id("DI"));
2470 CellInfo *pio = net_driven_by(ctx, d, is_trellis_io, id_O);
2471 if (pio != nullptr && d->users.size() == 1) {
2472 // Input FF
2473 CellInfo *iol;
2474 if (pio_iologic.count(pio->name))
2475 iol = pio_iologic.at(pio->name);
2476 else
2477 iol = create_pio_iologic(pio, ci);
2478 set_iologic_mode(iol, "IREG_OREG");
2479 set_iologic_sclk(iol, ci, ctx->id("CLK"), true);
2480 set_iologic_lsr(iol, ci, ctx->id("LSR"), true);
2481 // Handle CLK and CE muxes
2482 if (str_or_default(ci->params, ctx->id("CLKMUX")) == "INV")
2483 iol->params[ctx->id("CLKIMUX")] = std::string("INV");
2484 if (str_or_default(ci->params, ctx->id("CEMUX"), "CE") == "CE") {
2485 iol->params[ctx->id("CEIMUX")] = std::string("CEMUX");
2486 iol->params[ctx->id("CEMUX")] = std::string("CE");
2487 if (get_net_or_empty(ci, ctx->id("CE")) == nullptr)
2488 replace_port(ci, ctx->id("CE"), iol, ctx->id("CE"));
2489 else
2490 disconnect_port(ctx, ci, ctx->id("CE"));
2491 } else {
2492 iol->params[ctx->id("CEIMUX")] = std::string("1");
2493 }
2494 // Set IOLOGIC params from FF params
2495 iol->params[ctx->id("FF.INREGMODE")] = std::string("FF");
2496 iol->params[ctx->id("FF.REGSET")] = str_or_default(ci->params, ctx->id("REGSET"), "RESET");
2497 iol->params[ctx->id("SRMODE")] = str_or_default(ci->params, ctx->id("SRMODE"), "ASYNC");
2498 iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
2499 replace_port(ci, ctx->id("DI"), iol, id_PADDI);
2500 replace_port(ci, ctx->id("Q"), iol, id_INFF);
2501 packed_cells.insert(cell.first);
2502 continue;
2503 }
2504 }
2505 if (mode != "input") {
2506 CellInfo *pio_t = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_T, true);
2507 CellInfo *pio_i = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
2508 if (pio_t != nullptr || pio_i != nullptr) {
2509 // Output or tristate FF
2510 bool tri = (pio_t != nullptr);
2511 CellInfo *pio = tri ? pio_t : pio_i;
2512 CellInfo *iol;
2513 if (pio_iologic.count(pio->name))
2514 iol = pio_iologic.at(pio->name);
2515 else
2516 iol = create_pio_iologic(pio, ci);
2517 set_iologic_mode(iol, "IREG_OREG");
2518 // Connection between FF and PIO
2519 replace_port(ci, ctx->id("Q"), iol, tri ? id_IOLTO : id_IOLDO);
2520 if (tri) {
2521 if (!pio->ports.count(id_IOLTO)) {
2522 pio->ports[id_IOLTO].name = id_IOLTO;
2523 pio->ports[id_IOLTO].type = PORT_IN;
2524 }
2525 pio->params[ctx->id("TRIMUX_TSREG")] = std::string("IOLTO");
2526 replace_port(pio, id_T, pio, id_IOLTO);
2527 } else {
2528 if (!pio->ports.count(id_IOLDO)) {
2529 pio->ports[id_IOLDO].name = id_IOLDO;
2530 pio->ports[id_IOLDO].type = PORT_IN;
2531 }
2532 pio->params[ctx->id("DATAMUX_OREG")] = std::string("IOLDO");
2533 replace_port(pio, id_I, pio, id_IOLDO);
2534 }
2535
2536 set_iologic_sclk(iol, ci, ctx->id("CLK"), false);
2537 set_iologic_lsr(iol, ci, ctx->id("LSR"), false);
2538
2539 // Handle CLK and CE muxes
2540 if (str_or_default(ci->params, ctx->id("CLKMUX")) == "INV")
2541 iol->params[ctx->id("CLKOMUX")] = std::string("INV");
2542 if (str_or_default(ci->params, ctx->id("CEMUX"), "CE") == "CE") {
2543 iol->params[ctx->id("CEOMUX")] = std::string("CEMUX");
2544 iol->params[ctx->id("CEMUX")] = std::string("CE");
2545 if (get_net_or_empty(ci, ctx->id("CE")) == nullptr)
2546 replace_port(ci, ctx->id("CE"), iol, ctx->id("CE"));
2547 else
2548 disconnect_port(ctx, ci, ctx->id("CE"));
2549 } else {
2550 iol->params[ctx->id("CEOMUX")] = std::string("1");
2551 }
2552 // FF params
2553 iol->params[ctx->id(tri ? "TSREG.OUTREGMODE" : "OUTREG.OUTREGMODE")] = std::string("FF");
2554 iol->params[ctx->id(tri ? "TSREG.REGSET" : "OUTREG.REGSET")] =
2555 str_or_default(ci->params, ctx->id("REGSET"), "RESET");
2556 iol->params[ctx->id("SRMODE")] = str_or_default(ci->params, ctx->id("SRMODE"), "ASYNC");
2557 // Data input
2558 replace_port(ci, ctx->id("DI"), iol, tri ? id_TSDATA0 : id_TXDATA0);
2559 iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
2560 packed_cells.insert(cell.first);
2561 continue;
2562 }
2563 }
2564 log_error("Failed to pack flipflop '%s' with 'syn_useioff' set into IOLOGIC.\n", ci->name.c_str(ctx));
2565 }
2566 }
2567 flush_cells();
2568 // Constrain ECLK-related cells
2569 for (auto cell : sorted(ctx->cells)) {
2570 CellInfo *ci = cell.second;
2571 if (ci->type == id_ECLKBRIDGECS) {
2572 Loc loc;
2573 NetInfo *i0 = get_net_or_empty(ci, id_CLK0), *i1 = get_net_or_empty(ci, id_CLK1),
2574 *o = get_net_or_empty(ci, id_ECSOUT);
2575 for (NetInfo *input : {i0, i1}) {
2576 if (input == nullptr)
2577 continue;
2578 for (auto user : input->users) {
2579 if (!user.cell->attrs.count(ctx->id("BEL")))
2580 continue;
2581 Loc user_loc = ctx->getBelLocation(
2582 ctx->getBelByName(ctx->id(user.cell->attrs.at(ctx->id("BEL")).as_string())));
2583 for (auto bel : ctx->getBels()) {
2584 if (ctx->getBelType(bel) != id_ECLKBRIDGECS)
2585 continue;
2586 loc = ctx->getBelLocation(bel);
2587 if (loc.x == user_loc.x) {
2588 ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
2589 goto eclkbridge_done;
2590 }
2591 }
2592 }
2593 if (input->driver.cell != nullptr) {
2594 CellInfo *drv = input->driver.cell;
2595 if (!drv->attrs.count(ctx->id("BEL")))
2596 continue;
2597 Loc drv_loc = ctx->getBelLocation(
2598 ctx->getBelByName(ctx->id(drv->attrs.at(ctx->id("BEL")).as_string())));
2599 BelId closest;
2600 int closest_x = -1; // aim for same side of chip
2601 for (auto bel : ctx->getBels()) {
2602 if (ctx->getBelType(bel) != id_ECLKBRIDGECS)
2603 continue;
2604 loc = ctx->getBelLocation(bel);
2605 if (closest_x == -1 || std::abs(loc.x - drv_loc.x) < std::abs(closest_x - drv_loc.x)) {
2606 closest_x = loc.x;
2607 closest = bel;
2608 }
2609 }
2610 NPNR_ASSERT(closest != BelId());
2611 loc = ctx->getBelLocation(closest);
2612 ci->attrs[ctx->id("BEL")] = ctx->getBelName(closest).str(ctx);
2613 goto eclkbridge_done;
2614 }
2615 }
2616 // If all else fails, place randomly
2617 for (auto bel : ctx->getBels()) {
2618 if (ctx->getBelType(bel) != id_ECLKBRIDGECS)
2619 continue;
2620 loc = ctx->getBelLocation(bel);
2621 ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
2622 }
2623 eclkbridge_done:
2624 if (o != nullptr)
2625 for (auto user2 : o->users) {
2626 // Set side hint to ensure edge clock choice is routeable
2627 if (user2.cell->type == id_ECLKSYNCB && user2.port == id_ECLKI) {
2628 NetInfo *synco = get_net_or_empty(user2.cell, id_ECLKO);
2629 if (synco != nullptr)
2630 bridge_side_hint[synco] = (loc.x > 1) ? 0 : 1;
2631 }
2632 }
2633 continue;
2634 }
2635 }
2636 // Promote/route edge clocks
2637 for (auto cell : sorted(ctx->cells)) {
2638 CellInfo *ci = cell.second;
2639 if (ci->type == id_IOLOGIC || ci->type == id_DQSBUFM) {
2640 if (!ci->ports.count(id_ECLK) || ci->ports.at(id_ECLK).net == nullptr)
2641 continue;
2642 BelId bel = ctx->getBelByName(ctx->id(str_or_default(ci->attrs, ctx->id("BEL"))));
2643 NPNR_ASSERT(bel != BelId());
2644 Loc pioLoc = ctx->getBelLocation(bel);
2645 if (ci->type == id_DQSBUFM)
2646 pioLoc.z -= 8;
2647 else
2648 pioLoc.z -= 4;
2649 BelId pioBel = ctx->getBelByLocation(pioLoc);
2650 NPNR_ASSERT(pioBel != BelId());
2651 int bank = ctx->getPioBelBank(pioBel);
2652 make_eclk(ci->ports.at(id_ECLK), ci, bel, bank);
2653 }
2654 }
2655 flush_cells();
2656 for (auto cell : sorted(ctx->cells)) {
2657 CellInfo *ci = cell.second;
2658 if (ci->type == id_CLKDIVF) {
2659 const NetInfo *clki = net_or_nullptr(ci, id_CLKI);
2660 for (auto &eclk : eclks) {
2661 if (eclk.second.unbuf == clki) {
2662 for (auto bel : ctx->getBels()) {
2663 if (ctx->getBelType(bel) != id_CLKDIVF)
2664 continue;
2665 Loc loc = ctx->getBelLocation(bel);
2666 // CLKDIVF for bank 6/7 on the left; for bank 2/3 on the right
2667 if (loc.x < 10 && eclk.first.first != 6 && eclk.first.first != 7)
2668 continue;
2669 // z-index of CLKDIVF must match index of ECLK
2670 if (loc.z != eclk.first.second)
2671 continue;
2672 ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
2673 make_eclk(ci->ports.at(id_CLKI), ci, bel, eclk.first.first);
2674 goto clkdiv_done;
2675 }
2676 }
2677 }
2678 clkdiv_done:
2679 continue;
2680 } else if (ci->type == id_ECLKSYNCB) {
2681 const NetInfo *eclki = net_or_nullptr(ci, id_ECLKI);
2682 const NetInfo *eclko = net_or_nullptr(ci, id_ECLKO);
2683 if (eclki != nullptr && eclki->driver.cell != nullptr) {
2684 if (eclki->driver.cell->type == id_ECLKBRIDGECS) {
2685 BelId bel =
2686 ctx->getBelByName(ctx->id(eclki->driver.cell->attrs.at(ctx->id("BEL")).as_string()));
2687 Loc loc = ctx->getBelLocation(bel);
2688 ci->attrs[ctx->id("BEL")] =
2689 ctx->getBelName(ctx->getBelByLocation(Loc(loc.x, loc.y, 15))).str(ctx);
2690 goto eclksync_done;
2691 }
2692 }
2693 if (eclko == nullptr)
2694 log_error("ECLKSYNCB '%s' has disconnected port ECLKO\n", ci->name.c_str(ctx));
2695 for (auto user : eclko->users) {
2696 if (user.cell->type == id_TRELLIS_ECLKBUF) {
2697 Loc eckbuf_loc = ctx->getBelLocation(
2698 ctx->getBelByName(ctx->id(user.cell->attrs.at(ctx->id("BEL")).as_string())));
2699 for (auto bel : ctx->getBels()) {
2700 if (ctx->getBelType(bel) != id_ECLKSYNCB)
2701 continue;
2702 Loc loc = ctx->getBelLocation(bel);
2703 if (loc.x == eckbuf_loc.x && loc.y == eckbuf_loc.y && loc.z == eckbuf_loc.z - 2) {
2704 ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
2705 goto eclksync_done;
2706 }
2707 }
2708 }
2709 }
2710 eclksync_done:
2711 continue;
2712 } else if (ci->type == ctx->id("DDRDLLA")) {
2713 ci->type = id_DDRDLL; // transform from Verilog to Bel name
2714 const NetInfo *clk = net_or_nullptr(ci, id_CLK);
2715 if (clk == nullptr)
2716 log_error("DDRDLLA '%s' has disconnected port CLK\n", ci->name.c_str(ctx));
2717
2718 bool left_bank_users = false, right_bank_users = false;
2719 // Check which side the delay codes (DDRDEL) are used on
2720 const NetInfo *ddrdel = net_or_nullptr(ci, id_DDRDEL);
2721 if (ddrdel != nullptr) {
2722 for (auto &usr : ddrdel->users) {
2723 const CellInfo *uc = usr.cell;
2724 if (uc->type != id_DQSBUFM || !uc->attrs.count(ctx->id("BEL")))
2725 continue;
2726 BelId dqsb_bel = ctx->getBelByName(ctx->id(uc->attrs.at(ctx->id("BEL")).as_string()));
2727 Loc dqsb_loc = ctx->getBelLocation(dqsb_bel);
2728 if (dqsb_loc.x > 15)
2729 right_bank_users = true;
2730 if (dqsb_loc.x < 15)
2731 left_bank_users = true;
2732 }
2733 }
2734
2735 if (left_bank_users && right_bank_users)
2736 log_error("DDRDLLA '%s' has DDRDEL uses on both sides of the chip.\n", ctx->nameOf(ci));
2737
2738 for (auto &eclk : eclks) {
2739 if (eclk.second.unbuf == clk) {
2740 for (auto bel : ctx->getBels()) {
2741 if (ctx->getBelType(bel) != id_DDRDLL)
2742 continue;
2743 Loc loc = ctx->getBelLocation(bel);
2744 if (loc.x > 15 && left_bank_users)
2745 continue;
2746 if (loc.x < 15 && right_bank_users)
2747 continue;
2748 int ddrdll_bank = -1;
2749 if (loc.x < 15 && loc.y < 15)
2750 ddrdll_bank = 7;
2751 else if (loc.x < 15 && loc.y > 15)
2752 ddrdll_bank = 6;
2753 else if (loc.x > 15 && loc.y < 15)
2754 ddrdll_bank = 2;
2755 else if (loc.x > 15 && loc.y > 15)
2756 ddrdll_bank = 3;
2757 if (eclk.first.first != ddrdll_bank)
2758 continue;
2759 log_info("Constraining DDRDLLA '%s' to bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(bel));
2760 ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
2761 make_eclk(ci->ports.at(id_CLK), ci, bel, eclk.first.first);
2762 goto ddrdll_done;
2763 }
2764 }
2765 }
2766 ddrdll_done:
2767 continue;
2768 }
2769 }
2770
2771 flush_cells();
2772 };
2773
generate_constraints()2774 void generate_constraints()
2775 {
2776 log_info("Generating derived timing constraints...\n");
2777 auto MHz = [&](delay_t a) { return 1000.0 / ctx->getDelayNS(a); };
2778
2779 auto equals_epsilon = [](delay_t a, delay_t b) { return (std::abs(a - b) / std::max(double(b), 1.0)) < 1e-3; };
2780
2781 std::unordered_set<IdString> user_constrained, changed_nets;
2782 for (auto &net : ctx->nets) {
2783 if (net.second->clkconstr != nullptr)
2784 user_constrained.insert(net.first);
2785 changed_nets.insert(net.first);
2786 }
2787 auto get_period = [&](CellInfo *ci, IdString port, delay_t &period) {
2788 if (!ci->ports.count(port))
2789 return false;
2790 NetInfo *from = ci->ports.at(port).net;
2791 if (from == nullptr || from->clkconstr == nullptr)
2792 return false;
2793 period = from->clkconstr->period.min_delay;
2794 return true;
2795 };
2796
2797 auto set_period = [&](CellInfo *ci, IdString port, delay_t period) {
2798 if (!ci->ports.count(port))
2799 return;
2800 NetInfo *to = ci->ports.at(port).net;
2801 if (to == nullptr)
2802 return;
2803 if (to->clkconstr != nullptr) {
2804 if (!equals_epsilon(to->clkconstr->period.min_delay, period) && user_constrained.count(to->name))
2805 log_warning(
2806 " Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
2807 "%.1f MHz.\n",
2808 MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx), MHz(period));
2809 return;
2810 }
2811 to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
2812 to->clkconstr->low.min_delay = period / 2;
2813 to->clkconstr->low.max_delay = period / 2;
2814 to->clkconstr->high.min_delay = period / 2;
2815 to->clkconstr->high.max_delay = period / 2;
2816 to->clkconstr->period.min_delay = period;
2817 to->clkconstr->period.max_delay = period;
2818 log_info(" Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.min_delay),
2819 to->name.c_str(ctx));
2820 changed_nets.insert(to->name);
2821 };
2822
2823 auto copy_constraint = [&](CellInfo *ci, IdString fromPort, IdString toPort, double ratio = 1.0) {
2824 if (!ci->ports.count(fromPort) || !ci->ports.count(toPort))
2825 return;
2826 NetInfo *from = ci->ports.at(fromPort).net, *to = ci->ports.at(toPort).net;
2827 if (from == nullptr || from->clkconstr == nullptr || to == nullptr)
2828 return;
2829 if (to->clkconstr != nullptr) {
2830 if (!equals_epsilon(to->clkconstr->period.min_delay,
2831 delay_t(from->clkconstr->period.min_delay / ratio)) &&
2832 user_constrained.count(to->name))
2833 log_warning(
2834 " Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
2835 "%.1f MHz.\n",
2836 MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx),
2837 MHz(delay_t(from->clkconstr->period.min_delay / ratio)));
2838 return;
2839 }
2840 to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
2841 to->clkconstr->low = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->low.min_delay) / ratio);
2842 to->clkconstr->high = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->high.min_delay) / ratio);
2843 to->clkconstr->period = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->period.min_delay) / ratio);
2844 log_info(" Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.min_delay),
2845 to->name.c_str(ctx));
2846 changed_nets.insert(to->name);
2847 };
2848
2849 // Run in a loop while constraints are changing to deal with dependencies
2850 // Iteration limit avoids hanging in crazy loopback situation (self-fed PLLs or dividers, etc)
2851 int iter = 0;
2852 const int itermax = 5000;
2853 while (!changed_nets.empty() && iter < itermax) {
2854 ++iter;
2855 std::unordered_set<IdString> changed_cells;
2856 for (auto net : changed_nets) {
2857 for (auto &user : ctx->nets.at(net)->users)
2858 if (user.port == id_CLKI || user.port == id_ECLKI || user.port == id_CLK0 || user.port == id_CLK1)
2859 changed_cells.insert(user.cell->name);
2860 auto &drv = ctx->nets.at(net)->driver;
2861 if (iter == 1 && drv.cell != nullptr && drv.port == id_OSC)
2862 changed_cells.insert(drv.cell->name);
2863 }
2864 changed_nets.clear();
2865 for (auto cell : sorted(changed_cells)) {
2866 CellInfo *ci = ctx->cells.at(cell).get();
2867 if (ci->type == id_CLKDIVF) {
2868 std::string div = str_or_default(ci->params, ctx->id("DIV"), "2.0");
2869 double ratio;
2870 if (div == "2.0")
2871 ratio = 1 / 2.0;
2872 else if (div == "3.5")
2873 ratio = 1 / 3.5;
2874 else
2875 log_error("Unsupported divider ratio '%s' on CLKDIVF '%s'\n", div.c_str(), ci->name.c_str(ctx));
2876 copy_constraint(ci, id_CLKI, id_CDIVX, ratio);
2877 } else if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF) {
2878 copy_constraint(ci, id_ECLKI, id_ECLKO, 1);
2879 } else if (ci->type == id_ECLKBRIDGECS) {
2880 copy_constraint(ci, id_CLK0, id_ECSOUT, 1);
2881 copy_constraint(ci, id_CLK1, id_ECSOUT, 1);
2882 } else if (ci->type == id_DCCA) {
2883 copy_constraint(ci, id_CLKI, id_CLKO, 1);
2884 } else if (ci->type == id_EHXPLLL) {
2885 delay_t period_in;
2886 if (!get_period(ci, id_CLKI, period_in))
2887 continue;
2888 log_info(" Input frequency of PLL '%s' is constrained to %.1f MHz\n", ci->name.c_str(ctx),
2889 MHz(period_in));
2890 double period_in_div = period_in * int_or_default(ci->params, ctx->id("CLKI_DIV"), 1);
2891 std::string path = str_or_default(ci->params, ctx->id("FEEDBK_PATH"), "CLKOP");
2892 int feedback_div = int_or_default(ci->params, ctx->id("CLKFB_DIV"), 1);
2893 if (path == "CLKOP" || path == "INT_OP")
2894 feedback_div *= int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1);
2895 else if (path == "CLKOS" || path == "INT_OS")
2896 feedback_div *= int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1);
2897 else if (path == "CLKOS2" || path == "INT_OS2")
2898 feedback_div *= int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1);
2899 else if (path == "CLKOS3" || path == "INT_OS3")
2900 feedback_div *= int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1);
2901 else {
2902 log_info(" Unable to determine output frequencies for PLL '%s' with FEEDBK_PATH=%s\n",
2903 ci->name.c_str(ctx), path.c_str());
2904 continue;
2905 }
2906 double vco_period = period_in_div / feedback_div;
2907 double vco_freq = MHz(vco_period);
2908 if (vco_freq < 400 || vco_freq > 800)
2909 log_info(" Derived VCO frequency %.1f MHz of PLL '%s' is out of legal range [400MHz, "
2910 "800MHz]\n",
2911 vco_freq, ci->name.c_str(ctx));
2912 set_period(ci, id_CLKOP, vco_period * int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1));
2913 set_period(ci, id_CLKOS, vco_period * int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1));
2914 set_period(ci, id_CLKOS2, vco_period * int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1));
2915 set_period(ci, id_CLKOS3, vco_period * int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1));
2916 } else if (ci->type == id_OSCG) {
2917 int div = int_or_default(ci->params, ctx->id("DIV"), 128);
2918 set_period(ci, id_OSC, delay_t((1.0e6 / (2.0 * 155)) * div));
2919 }
2920 }
2921 }
2922 }
2923
prepack_checks()2924 void prepack_checks()
2925 {
2926 // Check for legacy-style JSON (use CEMUX as a clue) and error out, avoiding a confusing assertion failure
2927 // later
2928 for (auto cell : sorted(ctx->cells)) {
2929 if (is_ff(ctx, cell.second) && cell.second->params.count(ctx->id("CEMUX")) &&
2930 !cell.second->params[ctx->id("CEMUX")].is_string)
2931 log_error("Found netlist using legacy-style JSON parameter values, please update your Yosys.\n");
2932 }
2933 }
2934
2935 public:
pack()2936 void pack()
2937 {
2938 prepack_checks();
2939 print_logic_usage();
2940 pack_io();
2941 pack_dqsbuf();
2942 preplace_plls();
2943 pack_iologic();
2944 pack_ebr();
2945 pack_dsps();
2946 pack_dcus();
2947 pack_misc();
2948 pack_constants();
2949 pack_dram();
2950 pack_carries();
2951 find_lutff_pairs();
2952 pack_lut5xs();
2953 pair_luts();
2954 pack_lut_pairs();
2955 pack_remaining_luts();
2956 pack_remaining_ffs();
2957 generate_constraints();
2958 promote_ecp5_globals(ctx);
2959 ctx->fixupHierarchy();
2960 ctx->check();
2961 }
2962
2963 private:
2964 Context *ctx;
2965
2966 std::unordered_set<IdString> packed_cells;
2967 std::vector<std::unique_ptr<CellInfo>> new_cells;
2968
2969 struct SliceUsage
2970 {
2971 bool lut0_used = false, lut1_used = false;
2972 bool ccu2_used = false, dpram_used = false, ramw_used = false;
2973 bool ff0_used = false, ff1_used = false;
2974 bool mux5_used = false, muxx_used = false;
2975 };
2976
2977 std::unordered_map<IdString, SliceUsage> sliceUsage;
2978 std::unordered_map<IdString, IdString> lutffPairs;
2979 std::unordered_map<IdString, IdString> fflutPairs;
2980 std::unordered_map<IdString, IdString> lutPairs;
2981 };
2982 // Main pack function
pack()2983 bool Arch::pack()
2984 {
2985 Context *ctx = getCtx();
2986 try {
2987 log_break();
2988 Ecp5Packer(ctx).pack();
2989 log_info("Checksum: 0x%08x\n", ctx->checksum());
2990 assignArchInfo();
2991 ctx->settings[ctx->id("pack")] = 1;
2992 archInfoToAttributes();
2993 return true;
2994 } catch (log_execution_error_exception) {
2995 assignArchInfo();
2996 return false;
2997 }
2998 }
2999
assignArchInfo()3000 void Arch::assignArchInfo()
3001 {
3002 for (auto cell : sorted(cells)) {
3003 CellInfo *ci = cell.second;
3004 if (ci->type == id_TRELLIS_SLICE) {
3005
3006 ci->sliceInfo.using_dff = false;
3007 if (ci->ports.count(id_Q0) && ci->ports[id_Q0].net != nullptr)
3008 ci->sliceInfo.using_dff = true;
3009 if (ci->ports.count(id_Q1) && ci->ports[id_Q1].net != nullptr)
3010 ci->sliceInfo.using_dff = true;
3011
3012 if (ci->ports.count(id_CLK) && ci->ports[id_CLK].net != nullptr)
3013 ci->sliceInfo.clk_sig = ci->ports[id_CLK].net->name;
3014 else
3015 ci->sliceInfo.clk_sig = IdString();
3016
3017 if (ci->ports.count(id_LSR) && ci->ports[id_LSR].net != nullptr)
3018 ci->sliceInfo.lsr_sig = ci->ports[id_LSR].net->name;
3019 else
3020 ci->sliceInfo.lsr_sig = IdString();
3021
3022 ci->sliceInfo.clkmux = id(str_or_default(ci->params, id_CLKMUX, "CLK"));
3023 ci->sliceInfo.lsrmux = id(str_or_default(ci->params, id_LSRMUX, "LSR"));
3024 ci->sliceInfo.srmode = id(str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
3025 ci->sliceInfo.is_carry = str_or_default(ci->params, id("MODE"), "LOGIC") == "CCU2";
3026 ci->sliceInfo.sd0 = std::stoi(str_or_default(ci->params, id("REG0_SD"), "0"));
3027 ci->sliceInfo.sd1 = std::stoi(str_or_default(ci->params, id("REG1_SD"), "0"));
3028 ci->sliceInfo.has_l6mux = false;
3029 if (ci->ports.count(id_FXA) && ci->ports[id_FXA].net != nullptr &&
3030 ci->ports[id_FXA].net->driver.port == id_OFX0)
3031 ci->sliceInfo.has_l6mux = true;
3032 } else if (ci->type == id_DP16KD) {
3033 ci->ramInfo.is_pdp = (int_or_default(ci->params, id("DATA_WIDTH_A"), 0) == 36);
3034
3035 // Output register mode (REGMODE_{A,B}). Valid options are 'NOREG' and 'OUTREG'.
3036 std::string regmode_a = str_or_default(ci->params, id("REGMODE_A"), "NOREG");
3037 if (regmode_a != "NOREG" && regmode_a != "OUTREG")
3038 log_error("DP16KD %s has invalid REGMODE_A configuration '%s'\n", ci->name.c_str(this),
3039 regmode_a.c_str());
3040 std::string regmode_b = str_or_default(ci->params, id("REGMODE_B"), "NOREG");
3041 if (regmode_b != "NOREG" && regmode_b != "OUTREG")
3042 log_error("DP16KD %s has invalid REGMODE_B configuration '%s'\n", ci->name.c_str(this),
3043 regmode_b.c_str());
3044 ci->ramInfo.is_output_a_registered = regmode_a == "OUTREG";
3045 ci->ramInfo.is_output_b_registered = regmode_b == "OUTREG";
3046
3047 // Based on the REGMODE, we have different timing lookup tables.
3048 if (!ci->ramInfo.is_output_a_registered && !ci->ramInfo.is_output_b_registered) {
3049 ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_NOREG_REGMODE_B_NOREG;
3050 } else if (!ci->ramInfo.is_output_a_registered && ci->ramInfo.is_output_b_registered) {
3051 ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_NOREG_REGMODE_B_OUTREG;
3052 } else if (ci->ramInfo.is_output_a_registered && !ci->ramInfo.is_output_b_registered) {
3053 ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_OUTREG_REGMODE_B_NOREG;
3054 } else if (ci->ramInfo.is_output_a_registered && ci->ramInfo.is_output_b_registered) {
3055 ci->ramInfo.regmode_timing_id = id_DP16KD_REGMODE_A_OUTREG_REGMODE_B_OUTREG;
3056 }
3057 } else if (ci->type == id_MULT18X18D) {
3058 // For the multiplier block, our timing db is dictated by whether any of the input/output registers are
3059 // enabled. To that end, we need to work out what the parameters are for the INPUTA_CLK, INPUTB_CLK and
3060 // OUTPUT_CLK are.
3061 // The clock check is the same IN_A/B and OUT, so hoist it to a function
3062 auto get_clock_parameter = [&](std::string param_name) {
3063 std::string clk = str_or_default(ci->params, id(param_name), "NONE");
3064 if (clk != "NONE" && clk != "CLK0" && clk != "CLK1" && clk != "CLK2" && clk != "CLK3")
3065 log_error("MULT18X18D %s has invalid %s configuration '%s'\n", ci->name.c_str(this),
3066 param_name.c_str(), clk.c_str());
3067 return clk;
3068 };
3069
3070 // Get the input clock setting from the cell
3071 std::string reg_inputa_clk = get_clock_parameter("REG_INPUTA_CLK");
3072 std::string reg_inputb_clk = get_clock_parameter("REG_INPUTB_CLK");
3073
3074 // Inputs are registered IFF the REG_INPUT value is not NONE
3075 const bool is_in_a_registered = reg_inputa_clk != "NONE";
3076 const bool is_in_b_registered = reg_inputb_clk != "NONE";
3077
3078 // Similarly, get the output register clock
3079 std::string reg_output_clk = get_clock_parameter("REG_OUTPUT_CLK");
3080 const bool is_output_registered = reg_output_clk != "NONE";
3081
3082 // If only one of the inputs is registered, we are going to treat that as
3083 // neither input registered so that we don't have to deal with mixed timing.
3084 // Emit a warning to that effect.
3085 const bool any_input_registered = is_in_a_registered || is_in_b_registered;
3086 const bool both_inputs_registered = is_in_a_registered && is_in_b_registered;
3087 const bool input_registers_mismatched = any_input_registered && !both_inputs_registered;
3088 if (input_registers_mismatched) {
3089 log_warning("MULT18X18D %s has unsupported mixed input register modes (reg_inputa_clk=%s, "
3090 "reg_inputb_clk=%s)\n",
3091 ci->name.c_str(this), reg_inputa_clk.c_str(), reg_inputb_clk.c_str());
3092 log_warning("Timings for MULT18X18D %s will be calculated as though neither input were registered\n",
3093 ci->name.c_str(this));
3094
3095 // Act as though the inputs are unregistered, so select timing DB based only on the
3096 // output register mode
3097 ci->multInfo.timing_id = is_output_registered ? id_MULT18X18D_REGS_OUTPUT : id_MULT18X18D_REGS_NONE;
3098 } else {
3099 // Based on our register settings, pick the timing data to use for this cell
3100 if (!both_inputs_registered && !is_output_registered) {
3101 ci->multInfo.timing_id = id_MULT18X18D_REGS_NONE;
3102 } else if (both_inputs_registered && !is_output_registered) {
3103 ci->multInfo.timing_id = id_MULT18X18D_REGS_INPUT;
3104 } else if (!both_inputs_registered && is_output_registered) {
3105 ci->multInfo.timing_id = id_MULT18X18D_REGS_OUTPUT;
3106 } else if (both_inputs_registered && is_output_registered) {
3107 ci->multInfo.timing_id = id_MULT18X18D_REGS_ALL;
3108 }
3109 }
3110 // If we aren't a pure combinatorial multiplier, then our timings are
3111 // calculated with respect to CLK0
3112 ci->multInfo.is_clocked = ci->multInfo.timing_id != id_MULT18X18D_REGS_NONE;
3113 }
3114 }
3115 for (auto net : sorted(nets)) {
3116 net.second->is_global = bool_or_default(net.second->attrs, id("ECP5_IS_GLOBAL"));
3117 }
3118 }
3119
3120 NEXTPNR_NAMESPACE_END
3121