Home
last modified time | relevance | path

Searched refs:ce_clk_ctrl (Results 1 – 25 of 126) sorted by relevance

123456

/dports/sysutils/u-boot-utilite/u-boot-2015.07/drivers/mmc/
H A Dsh_mmcif.c106 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
107 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
117 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
118 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
125 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
131 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/mmc/
H A Dsh_mmcif.c107 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
108 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
114 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
118 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
126 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
132 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/mmc/
H A Dsh_mmcif.c107 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
108 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
114 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
118 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
126 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
132 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/mmc/
H A Dsh_mmcif.c107 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
108 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
114 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
118 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
126 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
132 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/mmc/
H A Dsh_mmcif.c107 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
108 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
114 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
118 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
126 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
132 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/mmc/
H A Dsh_mmcif.c112 sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
113 sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
119 sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
123 &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
124 sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl); in sh_mmcif_clock_control()
131 tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE | in sh_mmcif_sync_reset()
137 &host->regs->ce_clk_ctrl); in sh_mmcif_sync_reset()

123456