Searched refs:clk64 (Results 1 – 4 of 4) sorted by relevance
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/toplevel/usrp_std/ |
| H A D | usrp_std.v | 72 wire clk64,clk128; net
105 assign clk64 = master_clk;
136 .txclk(clk64), .reset(tx_dsp_reset),
193 always @(posedge clk64)
201 always @(posedge clk64)
238 .rxclk(clk64),.rxstrobe(hb_strobe),
245 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
256 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
267 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
278 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
[all …]
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/toplevel/usrp_multi/ |
| H A D | usrp_multi.v | 73 wire clk64,clk128; net
114 assign clk64 = master_clk;
152 .txclk(clk64),.txstrobe(strobe_interp),
198 always @(posedge clk64)
207 always @(posedge clk64)
215 always @(posedge clk64)
263 .rxclk(clk64),.rxstrobe(hb_strobe),
270 ( .clock(clk64),.reset(reset_data),.enable(enable_rx),
281 ( .clock(clk64),.reset(reset_data),.enable(enable_rx),
334 ( .master_clk(clk64),.usbclk(usbclk),
[all …]
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/toplevel/mrfm/ |
| H A D | mrfm.v | 68 wire clk64; net
99 assign clk64 = master_clk;
111 …sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_d…
123 always @(posedge clk64)
127 …rx_dcoffset #(0)rx_dcoffset0(.clock(clk64),.enable(1'b1),.reset(reset),.adc_in(adc0),.adc_out(adc0…
132 mrfm_proc mrfm_proc(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx),
148 …setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr…
159 .rxclk(clk64),.rxstrobe(strobe_out),
170 ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
177 ( .master_clk(clk64),.usbclk(usbclk),
[all …]
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/toplevel/usrp_inband_usb/ |
| H A D | usrp_inband_usb.v | 67 wire clk64,clk128; net
142 .txclk(clk64),.txstrobe(strobe_interp),
171 .txclk(clk64),.txstrobe(strobe_interp),
225 always @(posedge clk64)
233 always @(posedge clk64)
269 .rxclk(clk64),.rxstrobe(hb_strobe),
293 .rxclk(clk64),.rxstrobe(hb_strobe),
300 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
311 ( .clock(clk64),.reset(1'b0),.enable(enable_rx),
394 assign clk64 = (timestop == 0) ? master_clk : 0;
[all …]
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