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Searched refs:clkset (Results 1 – 25 of 88) sorted by relevance

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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/arm/cpu/lh7a40x/
H A Dspeed.c58 maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11; in get_FCLK()
59 maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7; in get_FCLK()
60 prediv = (csc->clkset & CLKSET_PREDIV) >> 2; in get_FCLK()
61 ps = (csc->clkset & CLKSET_PS) >> 16; in get_FCLK()
73 return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1)); in get_HCLK()
82 (1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1))); in get_PCLK()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/arm/cpu/lh7a40x/
H A Dspeed.c58 maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11; in get_FCLK()
59 maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7; in get_FCLK()
60 prediv = (csc->clkset & CLKSET_PREDIV) >> 2; in get_FCLK()
61 ps = (csc->clkset & CLKSET_PS) >> 16; in get_FCLK()
73 return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1)); in get_HCLK()
82 (1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1))); in get_PCLK()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/arm/cpu/lh7a40x/
H A Dspeed.c58 maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11; in get_FCLK()
59 maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7; in get_FCLK()
60 prediv = (csc->clkset & CLKSET_PREDIV) >> 2; in get_FCLK()
61 ps = (csc->clkset & CLKSET_PS) >> 16; in get_FCLK()
73 return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1)); in get_HCLK()
82 (1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1))); in get_PCLK()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/cpu/lh7a40x/
H A Dspeed.c58 maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11; in get_FCLK()
59 maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7; in get_FCLK()
60 prediv = (csc->clkset & CLKSET_PREDIV) >> 2; in get_FCLK()
61 ps = (csc->clkset & CLKSET_PS) >> 16; in get_FCLK()
73 return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1)); in get_HCLK()
82 (1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1))); in get_PCLK()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/cpu/lh7a40x/
H A Dspeed.c58 maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11; in get_FCLK()
59 maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7; in get_FCLK()
60 prediv = (csc->clkset & CLKSET_PREDIV) >> 2; in get_FCLK()
61 ps = (csc->clkset & CLKSET_PS) >> 16; in get_FCLK()
73 return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1)); in get_HCLK()
82 (1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1))); in get_PCLK()
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/arm/cpu/lh7a40x/
H A Dspeed.c58 maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11; in get_FCLK()
59 maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7; in get_FCLK()
60 prediv = (csc->clkset & CLKSET_PREDIV) >> 2; in get_FCLK()
61 ps = (csc->clkset & CLKSET_PS) >> 16; in get_FCLK()
73 return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1)); in get_HCLK()
82 (1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1))); in get_PCLK()
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/arm/cpu/lh7a40x/
H A Dspeed.c58 maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11; in get_FCLK()
59 maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7; in get_FCLK()
60 prediv = (csc->clkset & CLKSET_PREDIV) >> 2; in get_FCLK()
61 ps = (csc->clkset & CLKSET_PS) >> 16; in get_FCLK()
73 return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1)); in get_HCLK()
82 (1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1))); in get_PCLK()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c29 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
31 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
33 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
34 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c44 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
46 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
47 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
48 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
49 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c44 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
46 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
47 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
48 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
49 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c29 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
31 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
33 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
34 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c29 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
31 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
33 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
34 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c29 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
31 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
33 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
34 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c29 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
31 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
33 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
34 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c29 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
31 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
33 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
34 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c29 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
31 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
33 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
34 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c44 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
46 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
47 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
48 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
49 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c44 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
46 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
47 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
48 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
49 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c29 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
31 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
33 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
34 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c29 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
31 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
33 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
34 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c29 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
31 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
33 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
34 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c29 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
31 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
33 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
34 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c29 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
31 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
33 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
34 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c29 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
31 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
33 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
34 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c29 const uint32_t clkset = readl(pllreg); in get_PLLCLK() local
31 rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1; in get_PLLCLK()
32 rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1; in get_PLLCLK()
33 do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */ in get_PLLCLK()
34 for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++) in get_PLLCLK()

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