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Searched refs:clkset1 (Results 1 – 25 of 140) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c61 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
63 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
64 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
75 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
77 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
78 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
89 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
91 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c61 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
63 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
64 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
75 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
77 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
78 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
89 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
91 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c61 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
63 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
64 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
75 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
77 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
78 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
89 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
91 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c61 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
63 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
64 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
75 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
77 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
78 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
89 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
91 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-qemu-riscv64/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c61 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
63 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
64 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
75 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
77 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
78 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
89 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
91 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dspeed.c46 const uint32_t clkset1 = readl(&syscon->clkset1); in get_FCLK() local
48 fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7]; in get_FCLK()
49 const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div; in get_FCLK()
60 const uint32_t clkset1 = readl(&syscon->clkset1); in get_HCLK() local
62 hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7]; in get_HCLK()
63 const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div; in get_HCLK()
74 const uint32_t clkset1 = readl(&syscon->clkset1); in get_PCLK() local
76 pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3]; in get_PCLK()

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