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Searched refs:cm_base (Results 1 – 25 of 54) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/arch/arm/mach-integrator/
H A Dcore.c34 static void __iomem *cm_base; variable
41 return readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET); in cm_get()
55 val = readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET) & ~mask; in cm_control()
56 writel(val | set, cm_base + INTEGRATOR_HDR_CTRL_OFFSET); in cm_control()
63 writel(0xffffffffU, cm_base + INTEGRATOR_HDR_IC_OFFSET + in cm_clear_irqs()
80 cm_base = of_iomap(cm, 0); in cm_init()
81 if (!cm_base) { in cm_init()
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/arm/mach-integrator/
H A Dcore.c34 static void __iomem *cm_base; variable
41 return readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET); in cm_get()
55 val = readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET) & ~mask; in cm_control()
56 writel(val | set, cm_base + INTEGRATOR_HDR_CTRL_OFFSET); in cm_control()
63 writel(0xffffffffU, cm_base + INTEGRATOR_HDR_IC_OFFSET + in cm_clear_irqs()
80 cm_base = of_iomap(cm, 0); in cm_init()
81 if (!cm_base) { in cm_init()
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/arm/mach-integrator/
H A Dcore.c34 static void __iomem *cm_base; variable
41 return readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET); in cm_get()
55 val = readl(cm_base + INTEGRATOR_HDR_CTRL_OFFSET) & ~mask; in cm_control()
56 writel(val | set, cm_base + INTEGRATOR_HDR_CTRL_OFFSET); in cm_control()
63 writel(0xffffffffU, cm_base + INTEGRATOR_HDR_IC_OFFSET + in cm_clear_irqs()
80 cm_base = of_iomap(cm, 0); in cm_init()
81 if (!cm_base) { in cm_init()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/versatile/
H A Dclk-versatile.c21 static void __iomem *cm_base; variable
63 if (!cm_base) { in cm_osc_setup()
72 cm_base = of_iomap(parent, 0); in cm_osc_setup()
74 if (!cm_base) { in cm_osc_setup()
81 clk = icst_clk_register(NULL, desc, clk_name, parent_name, cm_base); in cm_osc_setup()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/versatile/
H A Dclk-versatile.c21 static void __iomem *cm_base; variable
63 if (!cm_base) { in cm_osc_setup()
72 cm_base = of_iomap(parent, 0); in cm_osc_setup()
74 if (!cm_base) { in cm_osc_setup()
81 clk = icst_clk_register(NULL, desc, clk_name, parent_name, cm_base); in cm_osc_setup()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/versatile/
H A Dclk-versatile.c21 static void __iomem *cm_base; variable
63 if (!cm_base) { in cm_osc_setup()
72 cm_base = of_iomap(parent, 0); in cm_osc_setup()
74 if (!cm_base) { in cm_osc_setup()
81 clk = icst_clk_register(NULL, desc, clk_name, parent_name, cm_base); in cm_osc_setup()
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/arm/mach-omap2/
H A Dcm_common.c32 struct omap_domain_base cm_base; variable
49 cm_base.va = cm; in omap2_set_globals_cm()
77 *prcm_inst -= cm_base.offset; in cm_split_idlest_reg()
340 mem = &cm_base; in omap2_cm_base_init()
356 (cm_base.va && cm2_base.va))) in omap2_cm_base_init()
H A Dcm2xxx_3xxx.h52 return readl_relaxed(cm_base.va + module + idx); in omap2_cm_read_mod_reg()
57 writel_relaxed(val, cm_base.va + module + idx); in omap2_cm_write_mod_reg()
H A Dcm33xx.c53 return readl_relaxed(cm_base.va + inst + idx); in am33xx_cm_read_reg()
59 writel_relaxed(val, cm_base.va + inst + idx); in am33xx_cm_write_reg()
349 return cm_base.pa + inst + offset; in am33xx_cm_xlate_clkctrl()
H A Dcm.h27 extern struct omap_domain_base cm_base;
H A Dcminst44xx.c66 memcpy(&_cm_bases[OMAP4430_CM1_PARTITION], &cm_base, sizeof(cm_base)); in omap_cm_base_init()
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/arm/mach-omap2/
H A Dcm_common.c32 struct omap_domain_base cm_base; variable
49 cm_base.va = cm; in omap2_set_globals_cm()
77 *prcm_inst -= cm_base.offset; in cm_split_idlest_reg()
340 mem = &cm_base; in omap2_cm_base_init()
356 (cm_base.va && cm2_base.va))) in omap2_cm_base_init()
H A Dcm2xxx_3xxx.h52 return readl_relaxed(cm_base.va + module + idx); in omap2_cm_read_mod_reg()
57 writel_relaxed(val, cm_base.va + module + idx); in omap2_cm_write_mod_reg()
H A Dcm33xx.c53 return readl_relaxed(cm_base.va + inst + idx); in am33xx_cm_read_reg()
59 writel_relaxed(val, cm_base.va + inst + idx); in am33xx_cm_write_reg()
349 return cm_base.pa + inst + offset; in am33xx_cm_xlate_clkctrl()
H A Dcm.h27 extern struct omap_domain_base cm_base;
H A Dcminst44xx.c66 memcpy(&_cm_bases[OMAP4430_CM1_PARTITION], &cm_base, sizeof(cm_base)); in omap_cm_base_init()
/dports/multimedia/libv4l/linux-5.13-rc2/arch/arm/mach-omap2/
H A Dcm_common.c32 struct omap_domain_base cm_base; variable
49 cm_base.va = cm; in omap2_set_globals_cm()
77 *prcm_inst -= cm_base.offset; in cm_split_idlest_reg()
340 mem = &cm_base; in omap2_cm_base_init()
356 (cm_base.va && cm2_base.va))) in omap2_cm_base_init()
H A Dcm2xxx_3xxx.h52 return readl_relaxed(cm_base.va + module + idx); in omap2_cm_read_mod_reg()
57 writel_relaxed(val, cm_base.va + module + idx); in omap2_cm_write_mod_reg()
H A Dcm33xx.c53 return readl_relaxed(cm_base.va + inst + idx); in am33xx_cm_read_reg()
59 writel_relaxed(val, cm_base.va + inst + idx); in am33xx_cm_write_reg()
349 return cm_base.pa + inst + offset; in am33xx_cm_xlate_clkctrl()
H A Dcm.h27 extern struct omap_domain_base cm_base;
H A Dcminst44xx.c66 memcpy(&_cm_bases[OMAP4430_CM1_PARTITION], &cm_base, sizeof(cm_base)); in omap_cm_base_init()
/dports/emulators/qemu60/qemu-6.0.0/hw/mips/
H A Dboston.c279 const uint32_t cm_base = 0x16100000; in type_init() local
286 cm_base); in type_init()
290 cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS), in type_init()
295 cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS), in type_init()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/mips/
H A Dboston.c278 const uint32_t cm_base = 0x16100000; in type_init() local
285 cm_base); in type_init()
289 cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS), in type_init()
294 cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS), in type_init()
/dports/emulators/qemu42/qemu-4.2.1/include/hw/arm/
H A Dpxa.h151 hwaddr cm_base; member
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/include/hw/arm/
H A Dpxa.h150 hwaddr cm_base; member

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