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/dports/cad/iverilog/verilog-11.0/
H A Delaborate.cc5701 NetNet*condit_sig = 0; in elaborate() local
5710 condit_sig = tmp->synthesize(des, scope, tmp); in elaborate()
5711 ivl_assert(*condition, condit_sig); in elaborate()
5753 if (condit_sig) in elaborate()
5754 cerr << " if " << condit_sig->name(); in elaborate()
5779 src.size(), condit_sig, in elaborate()
5863 if (condit_sig) in elaborate()
5864 connect(condit_sig->pin(0), path->pin(idx)); in elaborate()