| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 44 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
62 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
63 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 44 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
62 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
63 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 44 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
62 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
63 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 44 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
62 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
63 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 44 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
62 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
63 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 44 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
62 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
63 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 44 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
62 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
63 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 28 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
46 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
47 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 28 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
46 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
47 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/m68k/cpu/mcf52x2/ |
| H A D | speed.c | 31 volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); in get_clocks() local
49 cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
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