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Searched refs:createDRegPairNode (Results 1 – 17 of 17) sorted by relevance

/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp237 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1591 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
2001 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2175 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
3245 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp235 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1532 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
1942 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2114 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
3102 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp235 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1533 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
1943 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2116 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
3096 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp300 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1798 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
2208 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2382 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
3734 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp300 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1798 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
2208 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2382 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
3734 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp300 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1798 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
2208 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2382 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
3734 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp320 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1845 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
2261 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2438 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
3993 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp320 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1845 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
2261 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2438 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
3993 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp320 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1845 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
2261 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2438 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
3993 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp320 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1845 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
2261 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2438 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
3993 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp320 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1845 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
2261 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2438 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
3993 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp336 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1861 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
2307 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2484 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
4320 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp336 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1861 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
2307 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2484 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
4320 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp332 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1857 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
2303 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2480 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
4316 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp336 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1862 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
2308 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2485 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
4325 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp336 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1861 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
2307 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2484 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
4320 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp336 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
1861 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) { in createDRegPairNode() function in ARMDAGToDAGISel
2307 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVST()
2484 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0); in SelectVLDSTLane()
4320 N, createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1))); in Select()