| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 149 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1069 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1118 SDValue RegSeq = createQTuple(Regs); in SelectTable()
1288 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
1310 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
1369 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
1408 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
1463 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
1492 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 144 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1038 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1087 SDValue RegSeq = createQTuple(Regs); in SelectTable()
1257 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
1279 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
1338 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
1377 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
1432 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
1461 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 144 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1038 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) {
1087 SDValue RegSeq = createQTuple(Regs);
1258 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1281 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1340 SDValue RegSeq = createQTuple(Regs);
1379 SDValue RegSeq = createQTuple(Regs);
1434 SDValue RegSeq = createQTuple(Regs);
1464 SDValue RegSeq = createQTuple(Regs);
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 199 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1126 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1175 SDValue RegSeq = createQTuple(Regs); in SelectTable()
1345 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
1367 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
1426 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
1465 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
1520 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
1549 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 199 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1126 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1175 SDValue RegSeq = createQTuple(Regs); in SelectTable()
1345 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
1367 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
1426 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
1465 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
1520 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
1549 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 199 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1126 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1175 SDValue RegSeq = createQTuple(Regs); in SelectTable()
1345 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
1367 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
1426 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
1465 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
1520 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
1549 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 231 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1196 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1255 SDValue RegSeq = createQTuple(Regs); in SelectTable()
1484 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
1548 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
1607 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
1646 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
1701 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
1730 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 225 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1191 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1250 SDValue RegSeq = createQTuple(Regs); in SelectTable()
1470 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
1535 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
1594 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
1633 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
1688 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
1717 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 265 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1233 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1292 SDValue RegSeq = createQTuple(Regs); in SelectTable()
1529 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
1593 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
1652 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
1691 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
1746 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
1775 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 231 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1196 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1255 SDValue RegSeq = createQTuple(Regs); in SelectTable()
1487 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
1551 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
1610 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
1649 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
1704 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
1733 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 225 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1190 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1249 SDValue RegSeq = createQTuple(Regs); in SelectTable()
1478 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
1542 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
1601 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
1640 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
1695 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
1724 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 265 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1233 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1292 SDValue RegSeq = createQTuple(Regs); in SelectTable()
1529 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
1593 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
1652 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
1691 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
1746 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
1775 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 265 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1233 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1292 SDValue RegSeq = createQTuple(Regs); in SelectTable()
1529 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
1593 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
1652 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
1691 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
1746 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
1775 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 265 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1233 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1292 SDValue RegSeq = createQTuple(Regs); in SelectTable()
1529 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
1593 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
1652 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
1691 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
1746 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
1775 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 265 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1233 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1292 SDValue RegSeq = createQTuple(Regs); in SelectTable()
1529 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
1593 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
1652 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
1691 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
1746 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
1775 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 231 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1196 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() function in AArch64DAGToDAGISel
1255 SDValue RegSeq = createQTuple(Regs); in SelectTable()
1487 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectStore()
1551 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs); in SelectPostStore()
1610 SDValue RegSeq = createQTuple(Regs); in SelectLoadLane()
1649 SDValue RegSeq = createQTuple(Regs); in SelectPostLoadLane()
1704 SDValue RegSeq = createQTuple(Regs); in SelectStoreLane()
1733 SDValue RegSeq = createQTuple(Regs); in SelectPostStoreLane()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 265 SDValue createQTuple(ArrayRef<SDValue> Vecs);
1233 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) {
1292 SDValue RegSeq = createQTuple(Regs);
1529 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1593 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
1652 SDValue RegSeq = createQTuple(Regs);
1691 SDValue RegSeq = createQTuple(Regs);
1746 SDValue RegSeq = createQTuple(Regs);
1775 SDValue RegSeq = createQTuple(Regs);
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 635 static Register createQTuple(ArrayRef<Register> Regs, MachineIRBuilder &MIB) { in createQTuple() function
4764 auto RegSeq = createQTuple(Regs, MIB); in selectShuffleVector()
5096 Register Tuple = Ty.getSizeInBits() == 128 ? createQTuple(Regs, MIB) in selectIntrinsicWithSideEffects()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 635 static Register createQTuple(ArrayRef<Register> Regs, MachineIRBuilder &MIB) { in createQTuple() function
4764 auto RegSeq = createQTuple(Regs, MIB); in selectShuffleVector()
5096 Register Tuple = Ty.getSizeInBits() == 128 ? createQTuple(Regs, MIB) in selectIntrinsicWithSideEffects()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 635 static Register createQTuple(ArrayRef<Register> Regs, MachineIRBuilder &MIB) { in createQTuple() function
4764 auto RegSeq = createQTuple(Regs, MIB); in selectShuffleVector()
5096 Register Tuple = Ty.getSizeInBits() == 128 ? createQTuple(Regs, MIB) in selectIntrinsicWithSideEffects()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 635 static Register createQTuple(ArrayRef<Register> Regs, MachineIRBuilder &MIB) { in createQTuple() function
4764 auto RegSeq = createQTuple(Regs, MIB); in selectShuffleVector()
5096 Register Tuple = Ty.getSizeInBits() == 128 ? createQTuple(Regs, MIB) in selectIntrinsicWithSideEffects()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 635 static Register createQTuple(ArrayRef<Register> Regs, MachineIRBuilder &MIB) { in createQTuple() function
4764 auto RegSeq = createQTuple(Regs, MIB); in selectShuffleVector()
5096 Register Tuple = Ty.getSizeInBits() == 128 ? createQTuple(Regs, MIB) in selectIntrinsicWithSideEffects()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 649 static Register createQTuple(ArrayRef<Register> Regs, MachineIRBuilder &MIB) { in createQTuple() function
4839 auto RegSeq = createQTuple(Regs, MIB); in selectShuffleVector()
5344 Register Tuple = Ty.getSizeInBits() == 128 ? createQTuple(Regs, MIB) in selectIntrinsicWithSideEffects()
|