/dports/sysutils/u-boot-chip/u-boot-2021.07/board/google/imx8mq_phanbell/ |
H A D | lpddr4_timing_1g.c | 104 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1722 .ddrphy_cfg = ddr_ddrphy_cfg, 1723 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/freescale/imx8mn_evk/ |
H A D | ddr4_timing.c | 110 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1045 .ddrphy_cfg = ddr_ddrphy_cfg, 1046 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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H A D | ddr4_timing_ld.c | 114 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1047 .ddrphy_cfg = ddr_ddrphy_cfg, 1048 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/google/imx8mq_phanbell/ |
H A D | lpddr4_timing_1g.c | 104 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1722 .ddrphy_cfg = ddr_ddrphy_cfg, 1723 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/technexion/pico-imx8mq/ |
H A D | lpddr4_timing_4gb.c | 106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1724 .ddrphy_cfg = ddr_ddrphy_cfg, 1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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H A D | lpddr4_timing_1gb.c | 106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1724 .ddrphy_cfg = ddr_ddrphy_cfg, 1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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H A D | lpddr4_timing_2gb.c | 106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1724 .ddrphy_cfg = ddr_ddrphy_cfg, 1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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H A D | lpddr4_timing_3gb.c | 106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1724 .ddrphy_cfg = ddr_ddrphy_cfg, 1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/technexion/pico-imx8mq/ |
H A D | lpddr4_timing_1gb.c | 106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1724 .ddrphy_cfg = ddr_ddrphy_cfg, 1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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H A D | lpddr4_timing_2gb.c | 106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1724 .ddrphy_cfg = ddr_ddrphy_cfg, 1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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H A D | lpddr4_timing_3gb.c | 106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1724 .ddrphy_cfg = ddr_ddrphy_cfg, 1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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H A D | lpddr4_timing_4gb.c | 106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1724 .ddrphy_cfg = ddr_ddrphy_cfg, 1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/google/imx8mq_phanbell/ |
H A D | lpddr4_timing_1g.c | 104 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1722 .ddrphy_cfg = ddr_ddrphy_cfg, 1723 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/freescale/imx8mn_evk/ |
H A D | ddr4_timing.c | 110 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1045 .ddrphy_cfg = ddr_ddrphy_cfg, 1046 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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H A D | ddr4_timing_ld.c | 114 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1047 .ddrphy_cfg = ddr_ddrphy_cfg, 1048 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/board/freescale/imx8mn_evk/ |
H A D | ddr4_timing.c | 110 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1045 .ddrphy_cfg = ddr_ddrphy_cfg, 1046 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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H A D | ddr4_timing_ld.c | 114 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1047 .ddrphy_cfg = ddr_ddrphy_cfg, 1048 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/board/technexion/pico-imx8mq/ |
H A D | lpddr4_timing_1gb.c | 106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1724 .ddrphy_cfg = ddr_ddrphy_cfg, 1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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H A D | lpddr4_timing_2gb.c | 106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1724 .ddrphy_cfg = ddr_ddrphy_cfg, 1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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H A D | lpddr4_timing_3gb.c | 106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1724 .ddrphy_cfg = ddr_ddrphy_cfg, 1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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H A D | lpddr4_timing_4gb.c | 106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1724 .ddrphy_cfg = ddr_ddrphy_cfg, 1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/board/google/imx8mq_phanbell/ |
H A D | lpddr4_timing_1g.c | 104 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1722 .ddrphy_cfg = ddr_ddrphy_cfg, 1723 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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/dports/sysutils/u-boot-wandboard/u-boot-2021.07/board/technexion/pico-imx8mq/ |
H A D | lpddr4_timing_4gb.c | 106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1724 .ddrphy_cfg = ddr_ddrphy_cfg, 1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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H A D | lpddr4_timing_3gb.c | 106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1724 .ddrphy_cfg = ddr_ddrphy_cfg, 1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/board/google/imx8mq_phanbell/ |
H A D | lpddr4_timing_1g.c | 104 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable 1722 .ddrphy_cfg = ddr_ddrphy_cfg, 1723 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
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