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Searched refs:ddr_ddrphy_cfg (Results 1 – 25 of 1184) sorted by relevance

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/dports/sysutils/u-boot-chip/u-boot-2021.07/board/google/imx8mq_phanbell/
H A Dlpddr4_timing_1g.c104 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1722 .ddrphy_cfg = ddr_ddrphy_cfg,
1723 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/freescale/imx8mn_evk/
H A Dddr4_timing.c110 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1045 .ddrphy_cfg = ddr_ddrphy_cfg,
1046 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
H A Dddr4_timing_ld.c114 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1047 .ddrphy_cfg = ddr_ddrphy_cfg,
1048 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/google/imx8mq_phanbell/
H A Dlpddr4_timing_1g.c104 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1722 .ddrphy_cfg = ddr_ddrphy_cfg,
1723 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/board/technexion/pico-imx8mq/
H A Dlpddr4_timing_4gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
H A Dlpddr4_timing_1gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
H A Dlpddr4_timing_2gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
H A Dlpddr4_timing_3gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/technexion/pico-imx8mq/
H A Dlpddr4_timing_1gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
H A Dlpddr4_timing_2gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
H A Dlpddr4_timing_3gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
H A Dlpddr4_timing_4gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/google/imx8mq_phanbell/
H A Dlpddr4_timing_1g.c104 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1722 .ddrphy_cfg = ddr_ddrphy_cfg,
1723 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/board/freescale/imx8mn_evk/
H A Dddr4_timing.c110 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1045 .ddrphy_cfg = ddr_ddrphy_cfg,
1046 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
H A Dddr4_timing_ld.c114 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1047 .ddrphy_cfg = ddr_ddrphy_cfg,
1048 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/board/freescale/imx8mn_evk/
H A Dddr4_timing.c110 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1045 .ddrphy_cfg = ddr_ddrphy_cfg,
1046 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
H A Dddr4_timing_ld.c114 struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1047 .ddrphy_cfg = ddr_ddrphy_cfg,
1048 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/board/technexion/pico-imx8mq/
H A Dlpddr4_timing_1gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
H A Dlpddr4_timing_2gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
H A Dlpddr4_timing_3gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
H A Dlpddr4_timing_4gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/board/google/imx8mq_phanbell/
H A Dlpddr4_timing_1g.c104 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1722 .ddrphy_cfg = ddr_ddrphy_cfg,
1723 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/board/technexion/pico-imx8mq/
H A Dlpddr4_timing_4gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
H A Dlpddr4_timing_3gb.c106 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1724 .ddrphy_cfg = ddr_ddrphy_cfg,
1725 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/board/google/imx8mq_phanbell/
H A Dlpddr4_timing_1g.c104 static struct dram_cfg_param ddr_ddrphy_cfg[] = { variable
1722 .ddrphy_cfg = ddr_ddrphy_cfg,
1723 .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),

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