| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 91 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
109 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
112 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
115 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
147 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
148 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
232 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
247 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 91 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
109 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
112 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
115 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
147 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
148 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
232 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
247 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 91 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
109 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
112 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
115 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
147 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
148 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
232 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
247 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 91 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
109 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
112 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
115 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
147 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
148 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
232 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
247 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
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| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
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| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
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| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk322x.c | 93 struct rk322x_ddr_phy *ddr_phy) in phy_pctrl_reset() argument
111 clrbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
114 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
117 setbits_le32(&ddr_phy->ddrphy_reg[0], in phy_pctrl_reset()
149 writel(tmp, &ddr_phy->ddrphy_reg[0x28]); in phy_dll_bypass_set()
150 writel(tmp, &ddr_phy->ddrphy_reg[0x38]); in phy_dll_bypass_set()
151 writel(tmp, &ddr_phy->ddrphy_reg[0x48]); in phy_dll_bypass_set()
152 writel(tmp, &ddr_phy->ddrphy_reg[0x58]); in phy_dll_bypass_set()
234 struct rk322x_ddr_phy *ddr_phy = chan->phy; in data_training() local
249 ret = readl(&ddr_phy->ddrphy_reg[0xff]); in data_training()
[all …]
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