| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 95 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
126 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
138 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
140 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 95 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
126 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
138 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
140 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
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| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 95 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
126 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
138 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
140 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 95 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
126 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
138 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
140 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/ram/rockchip/ |
| H A D | sdram_rk3188.c | 99 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) in ddr_reset() function
130 ddr_reset(cru, channel, 1, 1); in phy_pctrl_reset()
142 ddr_reset(cru, channel, 1, 0); in phy_pctrl_reset()
144 ddr_reset(cru, channel, 0, 0); in phy_pctrl_reset()
|