| /dports/lang/chez-scheme/ChezScheme-9.5.4/s/ |
| H A D | ppc32.ss | 553 (define load/store
588 (define-instruction value (load)
590 (load/store info x y w
593 (define-instruction effect (store)
595 (load/store info x y w
599 (define-instruction effect (store-with-update)
603 (define-instruction effect (load-single load-single->double load-double load-double->single
843 asm-fl-load/store
1683 (define asm-fl-load/store
2210 (define (move-registers regs fp-reg-count fp-regs load? offset e)
[all …]
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| H A D | x86_64.ss | 234 (define-syntax define-instruction
498 (define-instruction value (-)
733 (define-instruction value (load)
755 (define-instruction effect (store)
781 (define-instruction effect (load-single->double load-double->single)
785 (define-instruction effect (store-single->double)
789 (define-instruction effect (store-single store-double)
793 (define-instruction effect (load-double load-single)
1806 (define asm-store-single->double
1813 (define asm-fl-store
[all …]
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| H A D | x86.ss | 191 (define-syntax define-instruction
670 (define-instruction value (load)
692 (define-instruction effect (store)
745 (define-instruction effect (load-single->double load-double->single)
749 (define-instruction effect (store-single store-double)
753 (define-instruction effect (load-double load-single)
1712 (define asm-fl-store
1776 (define asm-store
2343 (define (move-registers regs fp-reg-count load? offset e)
2594 `(inline ,(make-info-load 'integer-8 #f) ,%store
[all …]
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| H A D | arm32.ss | 568 (define load/store
613 (define-instruction value (load)
624 (define-instruction effect (store)
643 [else (asm-fl-load/store op flreg)]))))
644 (define-instruction effect (load-single->double load-double->single store-single->double
729 …unsigned1 and skip the fxmin...but no point burdening instruction scheduler with an additional one…
901 asm-fl-load/store
1821 (define-who asm-fl-store/cvt
1831 (define-who asm-fl-load/store
1871 (define-who asm-store
[all …]
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| /dports/lang/racket-minimal/racket-8.3/src/ChezScheme/s/ |
| H A D | ppc32.ss | 421 (define load/store
456 (define-instruction value (load)
461 (define-instruction effect (store)
467 (define-instruction effect (store-with-update)
504 (define-instruction value (load-single->double)
508 (define-instruction effect (store-double->single)
529 (define-instruction value (fp+ fp- fp/ fp*)
533 (define-instruction pred (fp= fp< fp<=)
2276 (define load/store-integer
3058 ;; we push all of the int reg args with one push instruction and all of the
[all …]
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| H A D | arm64.ss | 346 (define load/store
390 (define-instruction value (load)
393 (load/store x y w type
401 (define-instruction effect (store)
404 (load/store x y w type
420 (define-instruction effect (store-double->single)
427 (define-instruction effect (store-single)
431 (define-instruction value (load-single)
468 (define-instruction value (fp+ fp- fp/ fp*)
476 (define-instruction pred (fp= fp< fp<=)
[all …]
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| H A D | x86_64.ss | 545 (define-instruction value (load)
567 (define-instruction effect (store)
593 (define-instruction value (load-single->double)
601 (define-instruction effect (store-double->single)
608 (define-instruction effect (store-single)
612 (define-instruction value (load-single)
638 (define-instruction value (fp+ fp- fp* fp/)
708 (define-instruction pred (fp= fp< fp<=)
1793 (define asm-store-single->double
1800 (define asm-store-single
[all …]
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| H A D | pb.ss | 22 ;; The pb binstruction set is load--store and vaguely similar to Arm.
28 ;; Each 32-bit instruction has one of these formats, shown in byte
291 (define load/store
322 (define-instruction value (load)
325 (load/store x y w
333 (define-instruction effect (store)
336 (load/store x y w
345 (define-instruction value (load-single->double)
348 (define-instruction effect (store-double->single)
409 (define-instruction value (fp+ fp- fp/ fp*)
[all …]
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| H A D | arm32.ss | 463 (define load/store
508 (define-instruction value (load)
519 (define-instruction effect (store)
531 (define-instruction value (load-single->double)
538 (define-instruction effect (store-double->single)
545 (define-instruction effect (store-single)
549 (define-instruction value (load-single)
594 (define-instruction value (fp+ fp- fp/ fp*)
612 (define-instruction pred (fp= fp< fp<=)
804 (define-instruction effect (store-store-fence)
[all …]
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| H A D | x86.ss | 458 (define-instruction value (load)
480 (define-instruction effect (store)
536 (define-instruction value (load-single->double)
540 (define-instruction effect (store-double->single)
566 (define-instruction value (fp+ fp- fp* fp/)
620 (define-instruction pred (fp= fp< fp<=)
1558 (define asm-store-single
1654 (define asm-store
2203 (define (move-registers regs fp-reg-count load? offset e)
2458 `(inline ,(make-info-load 'integer-8 #f) ,%store
[all …]
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| /dports/lang/racket/racket-8.3/src/ChezScheme/s/ |
| H A D | ppc32.ss | 421 (define load/store
456 (define-instruction value (load)
461 (define-instruction effect (store)
467 (define-instruction effect (store-with-update)
504 (define-instruction value (load-single->double)
508 (define-instruction effect (store-double->single)
529 (define-instruction value (fp+ fp- fp/ fp*)
533 (define-instruction pred (fp= fp< fp<=)
2276 (define load/store-integer
3058 ;; we push all of the int reg args with one push instruction and all of the
[all …]
|
| H A D | arm64.ss | 346 (define load/store
390 (define-instruction value (load)
393 (load/store x y w type
401 (define-instruction effect (store)
404 (load/store x y w type
420 (define-instruction effect (store-double->single)
427 (define-instruction effect (store-single)
431 (define-instruction value (load-single)
468 (define-instruction value (fp+ fp- fp/ fp*)
476 (define-instruction pred (fp= fp< fp<=)
[all …]
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| H A D | x86_64.ss | 545 (define-instruction value (load)
567 (define-instruction effect (store)
593 (define-instruction value (load-single->double)
601 (define-instruction effect (store-double->single)
608 (define-instruction effect (store-single)
612 (define-instruction value (load-single)
638 (define-instruction value (fp+ fp- fp* fp/)
708 (define-instruction pred (fp= fp< fp<=)
1793 (define asm-store-single->double
1800 (define asm-store-single
[all …]
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| H A D | pb.ss | 22 ;; The pb binstruction set is load--store and vaguely similar to Arm.
28 ;; Each 32-bit instruction has one of these formats, shown in byte
291 (define load/store
322 (define-instruction value (load)
325 (load/store x y w
333 (define-instruction effect (store)
336 (load/store x y w
345 (define-instruction value (load-single->double)
348 (define-instruction effect (store-double->single)
409 (define-instruction value (fp+ fp- fp/ fp*)
[all …]
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| H A D | arm32.ss | 463 (define load/store
508 (define-instruction value (load)
519 (define-instruction effect (store)
531 (define-instruction value (load-single->double)
538 (define-instruction effect (store-double->single)
545 (define-instruction effect (store-single)
549 (define-instruction value (load-single)
594 (define-instruction value (fp+ fp- fp/ fp*)
612 (define-instruction pred (fp= fp< fp<=)
804 (define-instruction effect (store-store-fence)
[all …]
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| H A D | x86.ss | 458 (define-instruction value (load)
480 (define-instruction effect (store)
536 (define-instruction value (load-single->double)
540 (define-instruction effect (store-double->single)
566 (define-instruction value (fp+ fp- fp* fp/)
620 (define-instruction pred (fp= fp< fp<=)
1558 (define asm-store-single
1654 (define asm-store
2203 (define (move-registers regs fp-reg-count load? offset e)
2458 `(inline ,(make-info-load 'integer-8 #f) ,%store
[all …]
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| /dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/X86/ |
| H A D | i386-shrink-wrapping.ll | 41 ; We are interested in the one with the call, so skip until the branch.
61 ; The eflags is used in the next instruction.
62 ; If that instruction disappear, we are not exercising the bug
74 define i32 @eflagsLiveInPrologue() #0 {
76 %tmp = load i32, i32* @a, align 4
81 store i1 true, i1* @d, align 1
85 %tmp1 = load i32, i32* @b, align 4
96 %.b3 = load i1, i1* @d, align 1
98 store i8 %tmp2, i8* @e, align 1
99 %tmp3 = load i8, i8* @e, align 1
[all …]
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| /dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/X86/ |
| H A D | i386-shrink-wrapping.ll | 41 ; We are interested in the one with the call, so skip until the branch.
61 ; The eflags is used in the next instruction.
62 ; If that instruction disappear, we are not exercising the bug
74 define i32 @eflagsLiveInPrologue() #0 {
76 %tmp = load i32, i32* @a, align 4
81 store i1 true, i1* @d, align 1
85 %tmp1 = load i32, i32* @b, align 4
96 %.b3 = load i1, i1* @d, align 1
98 store i8 %tmp2, i8* @e, align 1
99 %tmp3 = load i8, i8* @e, align 1
[all …]
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| /dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AArch64/GlobalISel/ |
| H A D | combiner-load-store-indexing.ll | 12 load volatile i8, i8* %next
27 load volatile i8, i8* %next
31 store volatile i8* %next, i8** undef
52 store volatile i8 0, i8* %next
57 ; would produce the value too late but only by one instruction.
65 store volatile i64* %next.p0, i64** %next
82 ; Materializing the base into a writable register (from sp/fp) would be just as
105 %val = load i8, i8* %next
106 store i8 %val, i8* @var
107 store i8* %next, i8** @varp8
[all …]
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| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| H A D | combiner-load-store-indexing.ll | 12 load volatile i8, i8* %next
27 load volatile i8, i8* %next
31 store volatile i8* %next, i8** undef
52 store volatile i8 0, i8* %next
57 ; would produce the value too late but only by one instruction.
65 store volatile i64* %next.p0, i64** %next
82 ; Materializing the base into a writable register (from sp/fp) would be just as
105 %val = load i8, i8* %next
106 store i8 %val, i8* @var
107 store i8* %next, i8** @varp8
[all …]
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| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-misched-basic-A53.ll | 5 ; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
19 define i32 @main() #0 {
38 %2 = load i32, i32* %i, align 4
43 %3 = load i32, i32* %i, align 4
58 %8 = load i32, i32* %i, align 4
83 ; after it, this test checks to make sure there are more than one.
92 define <4 x float> @neon4xfloat(<4 x float> %A, <4 x float> %B) {
110 …" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffe…
118 define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) {
136 define void @testResourceConflict(float* %ptr) {
[all …]
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| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-misched-basic-A53.ll | 5 ; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
19 define i32 @main() #0 {
38 %2 = load i32, i32* %i, align 4
43 %3 = load i32, i32* %i, align 4
58 %8 = load i32, i32* %i, align 4
83 ; after it, this test checks to make sure there are more than one.
92 define <4 x float> @neon4xfloat(<4 x float> %A, <4 x float> %B) {
110 …" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffe…
118 define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) {
136 define void @testResourceConflict(float* %ptr) {
[all …]
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| /dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AArch64/ |
| H A D | arm64-misched-basic-A53.ll | 5 ; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
19 define i32 @main() #0 {
38 %2 = load i32, i32* %i, align 4
43 %3 = load i32, i32* %i, align 4
58 %8 = load i32, i32* %i, align 4
83 ; after it, this test checks to make sure there are more than one.
92 define <4 x float> @neon4xfloat(<4 x float> %A, <4 x float> %B) {
110 …" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffe…
118 define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) {
136 define void @testResourceConflict(float* %ptr) {
[all …]
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| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-misched-basic-A53.ll | 5 ; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
19 define i32 @main() #0 {
38 %2 = load i32, i32* %i, align 4
43 %3 = load i32, i32* %i, align 4
58 %8 = load i32, i32* %i, align 4
83 ; after it, this test checks to make sure there are more than one.
92 define <4 x float> @neon4xfloat(<4 x float> %A, <4 x float> %B) {
110 …" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffe…
118 define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) {
136 define void @testResourceConflict(float* %ptr) {
[all …]
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| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AArch64/ |
| H A D | arm64-misched-basic-A53.ll | 5 ; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
19 define i32 @main() #0 {
38 %2 = load i32, i32* %i, align 4
43 %3 = load i32, i32* %i, align 4
58 %8 = load i32, i32* %i, align 4
83 ; after it, this test checks to make sure there are more than one.
92 define <4 x float> @neon4xfloat(<4 x float> %A, <4 x float> %B) {
110 …" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffe…
118 define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) {
136 define void @testResourceConflict(float* %ptr) {
[all …]
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