dpll_hz (reference) in projects: dports

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Searched refs:dpll_hz (Results 1 – 25 of 114) sorted by relevance

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/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/clk/rockchip/
H A D	clk_rk3308.c	117 if (!priv->dpll_hz) in rk3308_clk_get_pll_rate() 155 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_i2c_get_clk() 164 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_i2c_set_clk() 390 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_spi_get_clk() 399 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_spi_set_clk() 434 return DIV_TO_RATE(priv->dpll_hz, div); in rk3308_pwm_get_clk() 443 src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz); in rk3308_pwm_set_clk() 470 parent = priv->dpll_hz; in rk3308_vop_get_clk() 500 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk() 548 u32 div, con, parent = priv->dpll_hz; in rk3308_bus_get_clk() [all …]

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