| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-pinebook/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
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| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/mips/mach-mtmips/ |
| H A D | ddr_cal.c | 111 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
142 dqs_dly = INIT_DQS_VAL; in ddr_calibrate()
147 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
150 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
155 dqs_dly_tmp = dqs_dly | (dqs_coarse_max << (4 + shift)); in ddr_calibrate()
167 dqs_dly_tmp = dqs_dly; in ddr_calibrate()
173 dqs_dly_tmp = dqs_dly | (dqs_coarse_min << (4 + shift)); in ddr_calibrate()
195 dqs_dly |= ((dqs_coarse_val << 4) | dqs_fine_val) << shift; in ddr_calibrate()
199 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
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