| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 400 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
487 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
488 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 400 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
487 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
488 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
|
| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 400 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
487 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
488 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 400 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
487 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
488 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { variable
488 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; in emif_get_ext_phy_ctrl_const_regs()
489 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); in emif_get_ext_phy_ctrl_const_regs()
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