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Searched refs:ds_add_rtn_u64 (Results 1 – 25 of 203) sorted by relevance

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/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/
H A Datomic_optimizations_local_pointer.ll67 ; GCN: ds_add_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}[[value_lo]]:[[value_…
81 ; GCN: ds_add_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}{{[0-9]+}}:{{[0-9]+}}…
93 ; GCN: ds_add_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}{{[0-9]+}}:{{[0-9]+}}…
H A Dlocal-atomics64.ll34 ; GCN: ds_add_rtn_u64
51 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
67 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\…
80 ; GCN: ds_add_rtn_u64 {{.*}} offset:32
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_ds.s1815 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 label
1818 ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535 label
1821 ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535 label
1824 ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535 label
1827 ds_add_rtn_u64 v[5:6], v1, v[2:3] label
1830 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0 label
1833 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4 label
1836 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds label
H A Dgfx9_asm_ds.s1953 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 label
1956 ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535 label
1959 ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535 label
1962 ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535 label
1965 ds_add_rtn_u64 v[5:6], v1, v[2:3] label
1968 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0 label
1971 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4 label
1974 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds label
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_ds.s1815 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 label
1818 ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535 label
1821 ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535 label
1824 ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535 label
1827 ds_add_rtn_u64 v[5:6], v1, v[2:3] label
1830 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0 label
1833 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4 label
1836 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds label
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_ds.s1815 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 label
1818 ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535 label
1821 ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535 label
1824 ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535 label
1827 ds_add_rtn_u64 v[5:6], v1, v[2:3] label
1830 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0 label
1833 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4 label
1836 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds label
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_ds.s1815 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 label
1818 ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535 label
1821 ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535 label
1824 ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535 label
1827 ds_add_rtn_u64 v[5:6], v1, v[2:3] label
1830 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0 label
1833 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4 label
1836 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds label
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_ds.s1815 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 label
1818 ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535 label
1821 ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535 label
1824 ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535 label
1827 ds_add_rtn_u64 v[5:6], v1, v[2:3] label
1830 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0 label
1833 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4 label
1836 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds label
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/MC/AMDGPU/
H A Dgfx7_asm_ds.s1815 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 label
1818 ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535 label
1821 ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535 label
1824 ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535 label
1827 ds_add_rtn_u64 v[5:6], v1, v[2:3] label
1830 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0 label
1833 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4 label
1836 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds label
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_ds.s1815 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 label
1818 ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535 label
1821 ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535 label
1824 ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535 label
1827 ds_add_rtn_u64 v[5:6], v1, v[2:3] label
1830 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0 label
1833 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4 label
1836 ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds label
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dlocal-atomics64.ll47 ; GCN: ds_add_rtn_u64
64 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
80 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\…
93 ; GCN: ds_add_rtn_u64 {{.*}} offset:32
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dlocal-atomics64.ll47 ; GCN: ds_add_rtn_u64
64 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
80 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\…
93 ; GCN: ds_add_rtn_u64 {{.*}} offset:32
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dlocal-atomics64.ll47 ; GCN: ds_add_rtn_u64
64 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
80 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\…
93 ; GCN: ds_add_rtn_u64 {{.*}} offset:32
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dlocal-atomics64.ll47 ; GCN: ds_add_rtn_u64
64 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
80 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\…
93 ; GCN: ds_add_rtn_u64 {{.*}} offset:32
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dlocal-atomics64.ll47 ; GCN: ds_add_rtn_u64
64 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
80 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\…
93 ; GCN: ds_add_rtn_u64 {{.*}} offset:32
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dlocal-atomics64.ll47 ; GCN: ds_add_rtn_u64
64 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
80 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\…
93 ; GCN: ds_add_rtn_u64 {{.*}} offset:32
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dlocal-atomics64.ll47 ; GCN: ds_add_rtn_u64
64 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
80 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\…
93 ; GCN: ds_add_rtn_u64 {{.*}} offset:32
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dlocal-atomics64.ll47 ; GCN: ds_add_rtn_u64
64 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
80 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\…
93 ; GCN: ds_add_rtn_u64 {{.*}} offset:32
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dlocal-atomics64.ll47 ; GCN: ds_add_rtn_u64
64 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
80 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\…
93 ; GCN: ds_add_rtn_u64 {{.*}} offset:32
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dlocal-atomics64.ll47 ; GCN: ds_add_rtn_u64
64 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
80 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\…
93 ; GCN: ds_add_rtn_u64 {{.*}} offset:32
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dlocal-atomics64.ll47 ; GCN: ds_add_rtn_u64
64 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
80 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\…
93 ; GCN: ds_add_rtn_u64 {{.*}} offset:32
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dlocal-atomics64.ll47 ; GCN: ds_add_rtn_u64
64 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
80 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\…
93 ; GCN: ds_add_rtn_u64 {{.*}} offset:32
H A Datomic_optimizations_local_pointer.ll69 ; GCN: ds_add_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}[[value_lo]]:[[value_…
83 ; GCN: ds_add_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}{{[0-9]+}}:{{[0-9]+}}…
95 ; GCN: ds_add_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}{{[0-9]+}}:{{[0-9]+}}…
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dlocal-atomics64.ll47 ; GCN: ds_add_rtn_u64
64 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
80 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\…
93 ; GCN: ds_add_rtn_u64 {{.*}} offset:32
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/
H A Dlocal-atomics64.ll34 ; GCN: ds_add_rtn_u64
51 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}}…
67 ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\…
80 ; GCN: ds_add_rtn_u64 {{.*}} offset:32

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