/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | llvm.amdgcn.ds.fmax.ll | 17 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 25 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 59 ; GFX8-NEXT: ds_max_rtn_f32 v0, v1, v0 offset:512 102 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 109 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 178 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 185 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 259 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 266 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 336 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | llvm.amdgcn.ds.fmax.ll | 17 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 25 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 59 ; GFX8-NEXT: ds_max_rtn_f32 v0, v1, v0 offset:512 102 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 109 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 178 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 185 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 259 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 266 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 336 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | llvm.amdgcn.ds.fmax.ll | 17 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 25 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 59 ; GFX8-NEXT: ds_max_rtn_f32 v0, v1, v0 offset:512 102 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 109 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 178 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 185 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 259 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 266 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 336 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | llvm.amdgcn.ds.fmax.ll | 17 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 25 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 59 ; GFX8-NEXT: ds_max_rtn_f32 v0, v1, v0 offset:512 102 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 109 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 178 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 185 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 259 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 266 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 336 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | llvm.amdgcn.ds.fmax.ll | 17 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 25 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 59 ; GFX8-NEXT: ds_max_rtn_f32 v0, v1, v0 offset:512 102 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 109 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 178 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 185 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 259 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 266 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 336 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | llvm.amdgcn.ds.fmax.ll | 17 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 25 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 59 ; GFX8-NEXT: ds_max_rtn_f32 v0, v1, v0 offset:512 102 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 109 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 178 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 185 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 259 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 266 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 336 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | llvm.amdgcn.ds.fmax.ll | 17 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 25 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 59 ; GFX8-NEXT: ds_max_rtn_f32 v0, v1, v0 offset:512 102 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 109 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 178 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 185 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 259 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 266 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 336 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
H A D | llvm.amdgcn.ds.fmax.ll | 17 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 25 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 59 ; GFX8-NEXT: ds_max_rtn_f32 v0, v1, v0 offset:512 102 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 109 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 178 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 185 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 259 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 266 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 336 ; GFX8-NEXT: ds_max_rtn_f32 v0, v0, v1 [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/ |
H A D | lds-atomic-fmin-fmax.ll | 328 ; SI-NEXT: ds_max_rtn_f32 v1, v1, v0 334 ; SI-NEXT: ds_max_rtn_f32 v0, v0, v1 361 ; GFX7-NEXT: ds_max_rtn_f32 v0, v0, v1 388 ; VI-NEXT: ds_max_rtn_f32 v0, v0, v1 414 ; GFX9-NEXT: ds_max_rtn_f32 v0, v0, v1 464 ; G_SI-NEXT: ds_max_rtn_f32 v1, v1, v0 467 ; G_SI-NEXT: ds_max_rtn_f32 v0, v2, v0 470 ; G_SI-NEXT: ds_max_rtn_f32 v0, v0, v1 520 ; G_VI-NEXT: ds_max_rtn_f32 v1, v1, v0 523 ; G_VI-NEXT: ds_max_rtn_f32 v0, v2, v0 [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/ |
H A D | lds_atomic_f32.ll | 54 ; GCN: ds_max_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32 57 ; GCN: ds_max_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/ |
H A D | lds_atomic_f32.ll | 54 ; GCN: ds_max_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32 57 ; GCN: ds_max_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | lds_atomic_f32.ll | 54 ; GCN: ds_max_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32 57 ; GCN: ds_max_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/ |
H A D | lds_atomic_f32.ll | 54 ; GCN: ds_max_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32 57 ; GCN: ds_max_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | lds_atomic_f32.ll | 54 ; GCN: ds_max_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32 57 ; GCN: ds_max_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/ |
H A D | lds_atomic_f32.ll | 54 ; GCN: ds_max_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32 57 ; GCN: ds_max_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/ |
H A D | lds_atomic_f32.ll | 54 ; GCN: ds_max_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32 57 ; GCN: ds_max_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | lds_atomic_f32.ll | 54 ; GCN: ds_max_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32 57 ; GCN: ds_max_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | lds_atomic_f32.ll | 54 ; GCN: ds_max_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32 57 ; GCN: ds_max_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/ |
H A D | lds_atomic_f32.ll | 54 ; GCN: ds_max_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32 57 ; GCN: ds_max_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/ |
H A D | lds_atomic_f32.ll | 54 ; GCN: ds_max_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32 57 ; GCN: ds_max_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/ |
H A D | lds_atomic_f32.ll | 54 ; GCN: ds_max_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32 57 ; GCN: ds_max_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/ |
H A D | lds_atomic_f32.ll | 54 ; GCN: ds_max_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32 57 ; GCN: ds_max_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/ |
H A D | lds_atomic_f32.ll | 54 ; GCN: ds_max_rtn_f32 [[V2:v[0-9]+]], [[V1:v[0-9]+]], [[V0]] offset:32 57 ; GCN: ds_max_rtn_f32 {{v[0-9]+}}, {{v[0-9]+}}, [[V2]]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/MC/AMDGPU/ |
H A D | gfx7_asm_ds.s | 1071 ds_max_rtn_f32 v5, v1, v2 offset:65535 label 1074 ds_max_rtn_f32 v255, v1, v2 offset:65535 label 1077 ds_max_rtn_f32 v5, v255, v2 offset:65535 label 1080 ds_max_rtn_f32 v5, v1, v255 offset:65535 label 1083 ds_max_rtn_f32 v5, v1, v2 label 1086 ds_max_rtn_f32 v5, v1, v2 offset:0 label 1089 ds_max_rtn_f32 v5, v1, v2 offset:4 label 1092 ds_max_rtn_f32 v5, v1, v2 offset:65535 gds label
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/MC/AMDGPU/ |
H A D | gfx7_asm_ds.s | 1071 ds_max_rtn_f32 v5, v1, v2 offset:65535 label 1074 ds_max_rtn_f32 v255, v1, v2 offset:65535 label 1077 ds_max_rtn_f32 v5, v255, v2 offset:65535 label 1080 ds_max_rtn_f32 v5, v1, v255 offset:65535 label 1083 ds_max_rtn_f32 v5, v1, v2 label 1086 ds_max_rtn_f32 v5, v1, v2 offset:0 label 1089 ds_max_rtn_f32 v5, v1, v2 offset:4 label 1092 ds_max_rtn_f32 v5, v1, v2 offset:65535 gds label
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