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Searched refs:ds_write_b64 (Results 1 – 25 of 531) sorted by relevance

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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dsplit-vector-memoperand-offsets.ll8 ; GCN-DAG: ds_write_b64 [[PTR:v[0-9]+]], [[VAL:v\[[0-9]+:[0-9]+\]]] offset:24
9 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:16
10 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:8
11 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]]{{$}}
15 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
16 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
17 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
19 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
H A Dindirect-private-64.ll19 ; SI-PROMOTE: ds_write_b64
21 ; CI-PROMOTE: ds_write_b64
48 ; SI-PROMOTE: ds_write_b64
49 ; SI-PROMOTE: ds_write_b64
76 ; SI-PROMOTE: ds_write_b64
78 ; CI-PROMOTE: ds_write_b64
106 ; SI-PROMOTE: ds_write_b64
107 ; SI-PROMOTE: ds_write_b64
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dsplit-vector-memoperand-offsets.ll8 ; GCN-DAG: ds_write_b64 [[PTR:v[0-9]+]], [[VAL:v\[[0-9]+:[0-9]+\]]] offset:24
9 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:16
10 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:8
11 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]]{{$}}
15 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
16 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
17 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
19 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
H A Dindirect-private-64.ll19 ; SI-PROMOTE: ds_write_b64
21 ; CI-PROMOTE: ds_write_b64
48 ; SI-PROMOTE: ds_write_b64
49 ; SI-PROMOTE: ds_write_b64
76 ; SI-PROMOTE: ds_write_b64
78 ; CI-PROMOTE: ds_write_b64
106 ; SI-PROMOTE: ds_write_b64
107 ; SI-PROMOTE: ds_write_b64
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dsplit-vector-memoperand-offsets.ll8 ; GCN-DAG: ds_write_b64 [[PTR:v[0-9]+]], [[VAL:v\[[0-9]+:[0-9]+\]]] offset:24
9 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:16
10 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:8
11 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]]{{$}}
15 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
16 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
17 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
19 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
H A Dindirect-private-64.ll19 ; SI-PROMOTE: ds_write_b64
21 ; CI-PROMOTE: ds_write_b64
48 ; SI-PROMOTE: ds_write_b64
49 ; SI-PROMOTE: ds_write_b64
76 ; SI-PROMOTE: ds_write_b64
78 ; CI-PROMOTE: ds_write_b64
106 ; SI-PROMOTE: ds_write_b64
107 ; SI-PROMOTE: ds_write_b64
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dsplit-vector-memoperand-offsets.ll8 ; GCN-DAG: ds_write_b64 [[PTR:v[0-9]+]], [[VAL:v\[[0-9]+:[0-9]+\]]] offset:24
9 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:16
10 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:8
11 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]]{{$}}
15 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
16 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
17 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
19 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
H A Dindirect-private-64.ll19 ; SI-PROMOTE: ds_write_b64
21 ; CI-PROMOTE: ds_write_b64
48 ; SI-PROMOTE: ds_write_b64
49 ; SI-PROMOTE: ds_write_b64
76 ; SI-PROMOTE: ds_write_b64
78 ; CI-PROMOTE: ds_write_b64
106 ; SI-PROMOTE: ds_write_b64
107 ; SI-PROMOTE: ds_write_b64
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dsplit-vector-memoperand-offsets.ll8 ; GCN-DAG: ds_write_b64 [[PTR:v[0-9]+]], [[VAL:v\[[0-9]+:[0-9]+\]]] offset:24
9 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:16
10 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:8
11 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]]{{$}}
15 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
16 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
17 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
19 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
H A Dindirect-private-64.ll19 ; SI-PROMOTE: ds_write_b64
21 ; CI-PROMOTE: ds_write_b64
48 ; SI-PROMOTE: ds_write_b64
49 ; SI-PROMOTE: ds_write_b64
76 ; SI-PROMOTE: ds_write_b64
78 ; CI-PROMOTE: ds_write_b64
106 ; SI-PROMOTE: ds_write_b64
107 ; SI-PROMOTE: ds_write_b64
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dsplit-vector-memoperand-offsets.ll8 ; GCN-DAG: ds_write_b64 [[PTR:v[0-9]+]], [[VAL:v\[[0-9]+:[0-9]+\]]] offset:24
9 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:16
10 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:8
11 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]]{{$}}
15 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
16 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
17 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
19 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
H A Dindirect-private-64.ll19 ; SI-PROMOTE: ds_write_b64
21 ; CI-PROMOTE: ds_write_b64
48 ; SI-PROMOTE: ds_write_b64
49 ; SI-PROMOTE: ds_write_b64
76 ; SI-PROMOTE: ds_write_b64
78 ; CI-PROMOTE: ds_write_b64
106 ; SI-PROMOTE: ds_write_b64
107 ; SI-PROMOTE: ds_write_b64
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dsplit-vector-memoperand-offsets.ll8 ; GCN-DAG: ds_write_b64 [[PTR:v[0-9]+]], [[VAL:v\[[0-9]+:[0-9]+\]]] offset:24
9 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:16
10 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:8
11 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]]{{$}}
15 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
16 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
17 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
19 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
H A Dindirect-private-64.ll19 ; SI-PROMOTE: ds_write_b64
21 ; CI-PROMOTE: ds_write_b64
48 ; SI-PROMOTE: ds_write_b64
49 ; SI-PROMOTE: ds_write_b64
76 ; SI-PROMOTE: ds_write_b64
78 ; CI-PROMOTE: ds_write_b64
106 ; SI-PROMOTE: ds_write_b64
107 ; SI-PROMOTE: ds_write_b64
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dsplit-vector-memoperand-offsets.ll8 ; GCN-DAG: ds_write_b64 [[PTR:v[0-9]+]], [[VAL:v\[[0-9]+:[0-9]+\]]] offset:24
9 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:16
10 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:8
11 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]]{{$}}
15 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
16 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
17 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
19 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
H A Dindirect-private-64.ll19 ; SI-PROMOTE: ds_write_b64
21 ; CI-PROMOTE: ds_write_b64
48 ; SI-PROMOTE: ds_write_b64
49 ; SI-PROMOTE: ds_write_b64
76 ; SI-PROMOTE: ds_write_b64
78 ; CI-PROMOTE: ds_write_b64
106 ; SI-PROMOTE: ds_write_b64
107 ; SI-PROMOTE: ds_write_b64
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dsplit-vector-memoperand-offsets.ll8 ; GCN-DAG: ds_write_b64 [[PTR:v[0-9]+]], [[VAL:v\[[0-9]+:[0-9]+\]]] offset:24
9 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:16
10 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:8
11 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]]{{$}}
15 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
16 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
17 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
19 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
H A Dindirect-private-64.ll19 ; SI-PROMOTE: ds_write_b64
21 ; CI-PROMOTE: ds_write_b64
48 ; SI-PROMOTE: ds_write_b64
49 ; SI-PROMOTE: ds_write_b64
76 ; SI-PROMOTE: ds_write_b64
78 ; CI-PROMOTE: ds_write_b64
106 ; SI-PROMOTE: ds_write_b64
107 ; SI-PROMOTE: ds_write_b64
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dsplit-vector-memoperand-offsets.ll8 ; GCN-DAG: ds_write_b64 [[PTR:v[0-9]+]], [[VAL:v\[[0-9]+:[0-9]+\]]] offset:24
9 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:16
10 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:8
11 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]]{{$}}
15 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
16 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
17 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
19 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dindirect-private-64.ll19 ; SI-PROMOTE: ds_write_b64
21 ; CI-PROMOTE: ds_write_b64
48 ; SI-PROMOTE: ds_write_b64
49 ; SI-PROMOTE: ds_write_b64
76 ; SI-PROMOTE: ds_write_b64
78 ; CI-PROMOTE: ds_write_b64
106 ; SI-PROMOTE: ds_write_b64
107 ; SI-PROMOTE: ds_write_b64
H A Dsplit-vector-memoperand-offsets.ll8 ; GCN-DAG: ds_write_b64 [[PTR:v[0-9]+]], [[VAL:v\[[0-9]+:[0-9]+\]]] offset:24
9 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:16
10 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:8
11 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]]{{$}}
15 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
16 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
17 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
19 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dsplit-vector-memoperand-offsets.ll8 ; GCN-DAG: ds_write_b64 [[PTR:v[0-9]+]], [[VAL:v\[[0-9]+:[0-9]+\]]] offset:24
9 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:16
10 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:8
11 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]]{{$}}
15 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
16 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
17 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
19 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}
H A Dindirect-private-64.ll19 ; SI-PROMOTE: ds_write_b64
21 ; CI-PROMOTE: ds_write_b64
48 ; SI-PROMOTE: ds_write_b64
49 ; SI-PROMOTE: ds_write_b64
76 ; SI-PROMOTE: ds_write_b64
78 ; CI-PROMOTE: ds_write_b64
106 ; SI-PROMOTE: ds_write_b64
107 ; SI-PROMOTE: ds_write_b64
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dindirect-private-64.ll19 ; SI-PROMOTE: ds_write_b64
21 ; CI-PROMOTE: ds_write_b64
48 ; SI-PROMOTE: ds_write_b64
49 ; SI-PROMOTE: ds_write_b64
76 ; SI-PROMOTE: ds_write_b64
78 ; CI-PROMOTE: ds_write_b64
106 ; SI-PROMOTE: ds_write_b64
107 ; SI-PROMOTE: ds_write_b64
H A Dsplit-vector-memoperand-offsets.ll8 ; GCN-DAG: ds_write_b64 [[PTR:v[0-9]+]], [[VAL:v\[[0-9]+:[0-9]+\]]] offset:24
9 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:16
10 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]] offset:8
11 ; GCN-DAG: ds_write_b64 [[PTR]], [[VAL]]{{$}}
15 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
16 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
17 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
19 ; GCN-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]$}}

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