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Searched refs:dst_rdy_int2 (Results 1 – 2 of 2) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/udp/
H A Dprot_eng_tx.v27 wire src_rdy_int2, dst_rdy_int2; net
69 if(src_rdy_int1 & dst_rdy_int2)
117 assign dst_rdy_int1 = dst_rdy_int2 & ((state == 0) | (state == 12));
123 .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/fifo/
H A Dfifo_2clock_cascade.v28 wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2; net
41 ….rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .occupied(l_…
46 .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),