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Searched refs:dv_pll0_regs (Results 1 – 25 of 69) sorted by relevance

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/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-davinci/
H A Ddm365_lowlevel.c32 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9); in dm365_pll1_init()
33 setbits_le32(&dv_pll0_regs->pllctl, in dm365_pll1_init()
43 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); in dm365_pll1_init()
48 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
53 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
56 writel(pllmult, &dv_pll0_regs->pllm); in dm365_pll1_init()
57 writel(prediv, &dv_pll0_regs->prediv); in dm365_pll1_init()
61 PLLSECCTL_TINITZ, &dv_pll0_regs->secctl); in dm365_pll1_init()
64 &dv_pll0_regs->secctl); in dm365_pll1_init()
71 writel(PLL_POSTDEN, &dv_pll0_regs->postdiv); in dm365_pll1_init()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-davinci/
H A Ddm365_lowlevel.c32 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9); in dm365_pll1_init()
33 setbits_le32(&dv_pll0_regs->pllctl, in dm365_pll1_init()
43 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); in dm365_pll1_init()
48 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
53 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
56 writel(pllmult, &dv_pll0_regs->pllm); in dm365_pll1_init()
57 writel(prediv, &dv_pll0_regs->prediv); in dm365_pll1_init()
61 PLLSECCTL_TINITZ, &dv_pll0_regs->secctl); in dm365_pll1_init()
64 &dv_pll0_regs->secctl); in dm365_pll1_init()
71 writel(PLL_POSTDEN, &dv_pll0_regs->postdiv); in dm365_pll1_init()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-davinci/
H A Ddm365_lowlevel.c32 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
33 setbits_le32(&dv_pll0_regs->pllctl,
43 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
48 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
53 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
56 writel(pllmult, &dv_pll0_regs->pllm);
57 writel(prediv, &dv_pll0_regs->prediv);
61 PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
64 &dv_pll0_regs->secctl);
71 writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-davinci/
H A Ddm365_lowlevel.c32 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9); in dm365_pll1_init()
33 setbits_le32(&dv_pll0_regs->pllctl, in dm365_pll1_init()
43 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); in dm365_pll1_init()
48 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
53 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
56 writel(pllmult, &dv_pll0_regs->pllm); in dm365_pll1_init()
57 writel(prediv, &dv_pll0_regs->prediv); in dm365_pll1_init()
61 PLLSECCTL_TINITZ, &dv_pll0_regs->secctl); in dm365_pll1_init()
64 &dv_pll0_regs->secctl); in dm365_pll1_init()
71 writel(PLL_POSTDEN, &dv_pll0_regs->postdiv); in dm365_pll1_init()
[all …]
/dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/mach-davinci/
H A Ddm365_lowlevel.c33 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9); in dm365_pll1_init()
34 setbits_le32(&dv_pll0_regs->pllctl, in dm365_pll1_init()
44 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); in dm365_pll1_init()
49 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
54 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
57 writel(pllmult, &dv_pll0_regs->pllm); in dm365_pll1_init()
58 writel(prediv, &dv_pll0_regs->prediv); in dm365_pll1_init()
62 PLLSECCTL_TINITZ, &dv_pll0_regs->secctl); in dm365_pll1_init()
65 &dv_pll0_regs->secctl); in dm365_pll1_init()
72 writel(PLL_POSTDEN, &dv_pll0_regs->postdiv); in dm365_pll1_init()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/mach-davinci/
H A Ddm365_lowlevel.c32 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9); in dm365_pll1_init()
33 setbits_le32(&dv_pll0_regs->pllctl, in dm365_pll1_init()
43 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); in dm365_pll1_init()
48 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
53 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
56 writel(pllmult, &dv_pll0_regs->pllm); in dm365_pll1_init()
57 writel(prediv, &dv_pll0_regs->prediv); in dm365_pll1_init()
61 PLLSECCTL_TINITZ, &dv_pll0_regs->secctl); in dm365_pll1_init()
64 &dv_pll0_regs->secctl); in dm365_pll1_init()
71 writel(PLL_POSTDEN, &dv_pll0_regs->postdiv); in dm365_pll1_init()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-davinci/include/mach/
H A Dpll_defs.h74 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE) macro

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