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/dports/devel/pear-PHPTAL/PHPTAL-1.3.0/tests/
H A DDomTest.php28 $el1 = $this->newElement();
34 $el1->appendChild($el2);
49 $el1->appendChild($ch);
72 $el1->appendChild($el2);
73 $el1->appendChild($el3);
74 $el1->appendChild($el4);
82 $el1->removeChild($el4);
91 $el1->removeChild($el2);
108 $el1->appendChild($el2);
109 $el1->appendChild($el3);
[all …]
/dports/java/eclipse/eclipse.platform.releng.aggregator-R4_16/rt.equinox.framework/bundles/org.eclipse.osgi.tests/src/org/eclipse/osgi/tests/eventmgr/
H A DEventManagerTests.java105 el1.putAll(el2); in testCopyOnWriteIdentityMap()
117 el2.putAll(el1); in testCopyOnWriteIdentityMap()
154 Set k1 = el1.keySet(); in testCopyOnWriteIdentityMap()
156 Set k3 = el1.keySet(); in testCopyOnWriteIdentityMap()
157 Set k4 = el1.keySet(); in testCopyOnWriteIdentityMap()
158 Collection v1 = el1.values(); in testCopyOnWriteIdentityMap()
162 Set e1 = el1.entrySet(); in testCopyOnWriteIdentityMap()
164 Set e3 = el1.entrySet(); in testCopyOnWriteIdentityMap()
165 Set e4 = el1.entrySet(); in testCopyOnWriteIdentityMap()
166 Set e5 = el1.entrySet(); in testCopyOnWriteIdentityMap()
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/AMDGPU/
H A Dfdot2.ll35 %mul1 = fmul half %src1.el1, %src2.el1
66 %csrc1.el1 = fpext half %src1.el1 to float
68 %csrc2.el1 = fpext half %src2.el1 to float
76 %mul1 = fmul float %csrc1.el1, %csrc2.el1
105 %csrc1.el1 = fpext half %src1.el1 to float
107 %csrc2.el1 = fpext half %src2.el1 to float
115 %mul1 = fmul float %csrc1.el1, %csrc2.el1
142 %csrc1.el1 = fpext half %src1.el1 to float
144 %csrc2.el1 = fpext half %src2.el1 to float
152 %mul1 = fmul float %csrc1.el1, %csrc2.el1
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/test/CodeGen/AMDGPU/
H A Dfdot2.ll35 %mul1 = fmul half %src1.el1, %src2.el1
66 %csrc1.el1 = fpext half %src1.el1 to float
68 %csrc2.el1 = fpext half %src2.el1 to float
76 %mul1 = fmul float %csrc1.el1, %csrc2.el1
105 %csrc1.el1 = fpext half %src1.el1 to float
107 %csrc2.el1 = fpext half %src2.el1 to float
115 %mul1 = fmul float %csrc1.el1, %csrc2.el1
142 %csrc1.el1 = fpext half %src1.el1 to float
144 %csrc2.el1 = fpext half %src2.el1 to float
152 %mul1 = fmul float %csrc1.el1, %csrc2.el1
[all …]
/dports/www/xist/ll-xist-5.34/test/
H A Dtest_xist_sims.py26 e = el1()
31 e = el1("gurk")
55 e = el1(el1())
169 e = el1()
172 e = el1("foo")
181 e = el1(el1())
188 e = el1(el2())
200 e = el1()
203 e = el1("foo")
215 e = el1(el1())
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/AMDGPU/
H A Dfdot2.ll38 %mul1 = fmul half %src1.el1, %src2.el1
70 %csrc1.el1 = fpext half %src1.el1 to float
72 %csrc2.el1 = fpext half %src2.el1 to float
80 %mul1 = fmul float %csrc1.el1, %csrc2.el1
110 %csrc1.el1 = fpext half %src1.el1 to float
112 %csrc2.el1 = fpext half %src2.el1 to float
120 %mul1 = fmul float %csrc1.el1, %csrc2.el1
147 %csrc1.el1 = fpext half %src1.el1 to float
149 %csrc2.el1 = fpext half %src2.el1 to float
157 %mul1 = fmul float %csrc1.el1, %csrc2.el1
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/AMDGPU/
H A Dfdot2.ll38 %mul1 = fmul half %src1.el1, %src2.el1
70 %csrc1.el1 = fpext half %src1.el1 to float
72 %csrc2.el1 = fpext half %src2.el1 to float
80 %mul1 = fmul float %csrc1.el1, %csrc2.el1
110 %csrc1.el1 = fpext half %src1.el1 to float
112 %csrc2.el1 = fpext half %src2.el1 to float
120 %mul1 = fmul float %csrc1.el1, %csrc2.el1
147 %csrc1.el1 = fpext half %src1.el1 to float
149 %csrc2.el1 = fpext half %src2.el1 to float
157 %mul1 = fmul float %csrc1.el1, %csrc2.el1
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/test/CodeGen/AMDGPU/
H A Dfdot2.ll38 %mul1 = fmul half %src1.el1, %src2.el1
70 %csrc1.el1 = fpext half %src1.el1 to float
72 %csrc2.el1 = fpext half %src2.el1 to float
80 %mul1 = fmul float %csrc1.el1, %csrc2.el1
110 %csrc1.el1 = fpext half %src1.el1 to float
112 %csrc2.el1 = fpext half %src2.el1 to float
120 %mul1 = fmul float %csrc1.el1, %csrc2.el1
147 %csrc1.el1 = fpext half %src1.el1 to float
149 %csrc2.el1 = fpext half %src2.el1 to float
157 %mul1 = fmul float %csrc1.el1, %csrc2.el1
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dfdot2.ll38 %mul1 = fmul half %src1.el1, %src2.el1
70 %csrc1.el1 = fpext half %src1.el1 to float
72 %csrc2.el1 = fpext half %src2.el1 to float
80 %mul1 = fmul float %csrc1.el1, %csrc2.el1
110 %csrc1.el1 = fpext half %src1.el1 to float
112 %csrc2.el1 = fpext half %src2.el1 to float
120 %mul1 = fmul float %csrc1.el1, %csrc2.el1
147 %csrc1.el1 = fpext half %src1.el1 to float
149 %csrc2.el1 = fpext half %src2.el1 to float
157 %mul1 = fmul float %csrc1.el1, %csrc2.el1
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/AMDGPU/
H A Dfdot2.ll38 %mul1 = fmul half %src1.el1, %src2.el1
70 %csrc1.el1 = fpext half %src1.el1 to float
72 %csrc2.el1 = fpext half %src2.el1 to float
80 %mul1 = fmul float %csrc1.el1, %csrc2.el1
110 %csrc1.el1 = fpext half %src1.el1 to float
112 %csrc2.el1 = fpext half %src2.el1 to float
120 %mul1 = fmul float %csrc1.el1, %csrc2.el1
147 %csrc1.el1 = fpext half %src1.el1 to float
149 %csrc2.el1 = fpext half %src2.el1 to float
157 %mul1 = fmul float %csrc1.el1, %csrc2.el1
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dfdot2.ll38 %mul1 = fmul half %src1.el1, %src2.el1
70 %csrc1.el1 = fpext half %src1.el1 to float
72 %csrc2.el1 = fpext half %src2.el1 to float
80 %mul1 = fmul float %csrc1.el1, %csrc2.el1
110 %csrc1.el1 = fpext half %src1.el1 to float
112 %csrc2.el1 = fpext half %src2.el1 to float
120 %mul1 = fmul float %csrc1.el1, %csrc2.el1
147 %csrc1.el1 = fpext half %src1.el1 to float
149 %csrc2.el1 = fpext half %src2.el1 to float
157 %mul1 = fmul float %csrc1.el1, %csrc2.el1
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/AMDGPU/
H A Dfdot2.ll38 %mul1 = fmul half %src1.el1, %src2.el1
70 %csrc1.el1 = fpext half %src1.el1 to float
72 %csrc2.el1 = fpext half %src2.el1 to float
80 %mul1 = fmul float %csrc1.el1, %csrc2.el1
110 %csrc1.el1 = fpext half %src1.el1 to float
112 %csrc2.el1 = fpext half %src2.el1 to float
120 %mul1 = fmul float %csrc1.el1, %csrc2.el1
147 %csrc1.el1 = fpext half %src1.el1 to float
149 %csrc2.el1 = fpext half %src2.el1 to float
157 %mul1 = fmul float %csrc1.el1, %csrc2.el1
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/AMDGPU/
H A Dfdot2.ll38 %mul1 = fmul half %src1.el1, %src2.el1
70 %csrc1.el1 = fpext half %src1.el1 to float
72 %csrc2.el1 = fpext half %src2.el1 to float
80 %mul1 = fmul float %csrc1.el1, %csrc2.el1
110 %csrc1.el1 = fpext half %src1.el1 to float
112 %csrc2.el1 = fpext half %src2.el1 to float
120 %mul1 = fmul float %csrc1.el1, %csrc2.el1
147 %csrc1.el1 = fpext half %src1.el1 to float
149 %csrc2.el1 = fpext half %src2.el1 to float
157 %mul1 = fmul float %csrc1.el1, %csrc2.el1
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dfdot2.ll38 %mul1 = fmul half %src1.el1, %src2.el1
70 %csrc1.el1 = fpext half %src1.el1 to float
72 %csrc2.el1 = fpext half %src2.el1 to float
80 %mul1 = fmul float %csrc1.el1, %csrc2.el1
110 %csrc1.el1 = fpext half %src1.el1 to float
112 %csrc2.el1 = fpext half %src2.el1 to float
120 %mul1 = fmul float %csrc1.el1, %csrc2.el1
147 %csrc1.el1 = fpext half %src1.el1 to float
149 %csrc2.el1 = fpext half %src2.el1 to float
157 %mul1 = fmul float %csrc1.el1, %csrc2.el1
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dfdot2.ll38 %mul1 = fmul half %src1.el1, %src2.el1
70 %csrc1.el1 = fpext half %src1.el1 to float
72 %csrc2.el1 = fpext half %src2.el1 to float
80 %mul1 = fmul float %csrc1.el1, %csrc2.el1
110 %csrc1.el1 = fpext half %src1.el1 to float
112 %csrc2.el1 = fpext half %src2.el1 to float
120 %mul1 = fmul float %csrc1.el1, %csrc2.el1
147 %csrc1.el1 = fpext half %src1.el1 to float
149 %csrc2.el1 = fpext half %src2.el1 to float
157 %mul1 = fmul float %csrc1.el1, %csrc2.el1
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dfdot2.ll38 %mul1 = fmul half %src1.el1, %src2.el1
70 %csrc1.el1 = fpext half %src1.el1 to float
72 %csrc2.el1 = fpext half %src2.el1 to float
80 %mul1 = fmul float %csrc1.el1, %csrc2.el1
110 %csrc1.el1 = fpext half %src1.el1 to float
112 %csrc2.el1 = fpext half %src2.el1 to float
120 %mul1 = fmul float %csrc1.el1, %csrc2.el1
147 %csrc1.el1 = fpext half %src1.el1 to float
149 %csrc2.el1 = fpext half %src2.el1 to float
157 %mul1 = fmul float %csrc1.el1, %csrc2.el1
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/test/CodeGen/AMDGPU/
H A Dfdot2.ll38 %mul1 = fmul half %src1.el1, %src2.el1
70 %csrc1.el1 = fpext half %src1.el1 to float
72 %csrc2.el1 = fpext half %src2.el1 to float
80 %mul1 = fmul float %csrc1.el1, %csrc2.el1
110 %csrc1.el1 = fpext half %src1.el1 to float
112 %csrc2.el1 = fpext half %src2.el1 to float
120 %mul1 = fmul float %csrc1.el1, %csrc2.el1
147 %csrc1.el1 = fpext half %src1.el1 to float
149 %csrc2.el1 = fpext half %src2.el1 to float
157 %mul1 = fmul float %csrc1.el1, %csrc2.el1
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/AMDGPU/
H A Dfdot2.ll38 %mul1 = fmul half %src1.el1, %src2.el1
70 %csrc1.el1 = fpext half %src1.el1 to float
72 %csrc2.el1 = fpext half %src2.el1 to float
80 %mul1 = fmul float %csrc1.el1, %csrc2.el1
110 %csrc1.el1 = fpext half %src1.el1 to float
112 %csrc2.el1 = fpext half %src2.el1 to float
120 %mul1 = fmul float %csrc1.el1, %csrc2.el1
147 %csrc1.el1 = fpext half %src1.el1 to float
149 %csrc2.el1 = fpext half %src2.el1 to float
157 %mul1 = fmul float %csrc1.el1, %csrc2.el1
[all …]
/dports/science/xdrawchem/xdrawchem-a3f74c34eb09fa72ee16848ec6901049ca5309d5/xdrawchem/
H A Dmoldata.h280 if (el1 > el2) {
281 swp = el1;
282 el1 = el2;
287 if (el1 == 1) {
298 if (el1 == 6) {
356 if (el1 == 6) {
366 if (el1 == 7) {
374 if (el1 == 8) {
380 if (el1 == 14) {
390 if (el1 == 15) {
[all …]
/dports/net-mgmt/wmi-client/wmi-1.3.16/Samba/source/lib/talloc/
H A Dtestsuite.c574 } *el1; in test_realloc_child() local
580 el1 = talloc(root, struct el1); in test_realloc_child()
581 el1->list = talloc(el1, struct el2 *); in test_realloc_child()
585 el1->list2 = talloc(el1, struct el2 *); in test_realloc_child()
589 el1->list3 = talloc(el1, struct el2 *); in test_realloc_child()
597 el1->list = talloc_realloc(el1, el1->list, struct el2 *, 100); in test_realloc_child()
598 el1->list2 = talloc_realloc(el1, el1->list2, struct el2 *, 200); in test_realloc_child()
599 el1->list3 = talloc_realloc(el1, el1->list3, struct el2 *, 300); in test_realloc_child()
619 struct el1 *el1; in test_type() local
625 el1 = talloc(root, struct el1); in test_type()
[all …]
/dports/devel/p5-VCS-Lite/VCS-Lite-0.12/t/
H A D21merge.t7 my $el1 = VCS::Lite->new('data/mariner.txt');
10 isa_ok($el1,'VCS::Lite','Return from new, passed filespec');
15 $el1->apply($el2);
18 ok(!$el1->delta($el2), "Not different once applied");
20 my $el1a = $el1->original;
23 ok($el1->delta($el1a), "but different from original");
29 $el1->apply($el1a, base => 'original');
31 my $merged = $el1->text;
/dports/textproc/py-docutils/docutils-0.17.1/build/lib/docutils/writers/odf_odt/
H A D__init__.py774 el1.text = s1
777 el1.text = s2
779 el1.text = s1
781 el1.text = s2
785 el1.text = '1'
1457 return el1
1950 el3 = el1
2215 el2 = el1
2550 el1 = el1[0][0]
3124 el2 = el1[0]
[all …]
/dports/textproc/py-docutils/docutils-0.17.1/docutils/writers/odf_odt/
H A D__init__.py774 el1.text = s1
777 el1.text = s2
779 el1.text = s1
781 el1.text = s2
785 el1.text = '1'
1457 return el1
1950 el3 = el1
2215 el2 = el1
2550 el1 = el1[0][0]
3124 el2 = el1[0]
[all …]
/dports/textproc/py-docutils/stage/usr/local/lib/python3.8/site-packages/docutils/writers/odf_odt/
H A D__init__.py774 el1.text = s1
777 el1.text = s2
779 el1.text = s1
781 el1.text = s2
785 el1.text = '1'
1457 return el1
1950 el3 = el1
2215 el2 = el1
2550 el1 = el1[0][0]
3124 el2 = el1[0]
[all …]
/dports/devel/pycharm-pro/pycharm-2020.2.3/plugins/python/helpers/py2only/docutils/writers/odf_odt/
H A D__init__.py694 el1.text = s1
697 el1.text = s2
699 el1.text = s1
701 el1.text = s2
705 el1.text = '1'
1355 el1 = None
1356 return el1
1841 el3 = el1
2104 el2 = el1
2363 el1 = el1[0][0]
[all …]

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