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/dports/textproc/xmlformat/xmlformat-1.04/
H A Dtest.conf9 elt1 elt2 elt3# comment
10 elt1 elt2 elt3 # comment
11 elt1,elt2,elt3# comment
12 elt1,elt2,elt3 # comment
/dports/sysutils/modules/modules-4.6.0/testsuite/bin/
H A Dinstall_test_cmake56 list(GET cmdelt 3 elt3)
59 module("${elt0}" "${elt1}" "${elt2}" "${elt3}" "${elt4}")
61 ml("${elt0}" "${elt1}" "${elt2}" "${elt3}" "${elt4}")
67 list(GET cmdelt 3 elt3)
69 module("${elt0}" "${elt1}" "${elt2}" "${elt3}")
71 ml("${elt0}" "${elt1}" "${elt2}" "${elt3}")
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll30 %add3 = fadd fast half %elt3, %add2
72 %add3 = fadd fast half %elt3, %add2
142 %add3 = fadd fast half %elt3, %add2
180 %add3 = fsub fast half %elt3, %add2
210 %add3 = add i16 %elt3, %add2
252 %add3 = add i16 %elt3, %add2
291 %cmp3 = icmp ult i16 %elt3, %min2
343 %cmp2 = icmp ult i16 %elt3, %min2
438 %cmp2 = icmp slt i16 %elt3, %min2
505 %cmp3 = icmp ugt i16 %elt3, %max2
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll30 %add3 = fadd fast half %elt3, %add2
72 %add3 = fadd fast half %elt3, %add2
142 %add3 = fadd fast half %elt3, %add2
180 %add3 = fsub fast half %elt3, %add2
210 %add3 = add i16 %elt3, %add2
252 %add3 = add i16 %elt3, %add2
291 %cmp3 = icmp ult i16 %elt3, %min2
343 %cmp2 = icmp ult i16 %elt3, %min2
438 %cmp2 = icmp slt i16 %elt3, %min2
505 %cmp3 = icmp ugt i16 %elt3, %max2
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll30 %add3 = fadd fast half %elt3, %add2
72 %add3 = fadd fast half %elt3, %add2
142 %add3 = fadd fast half %elt3, %add2
180 %add3 = fsub fast half %elt3, %add2
210 %add3 = add i16 %elt3, %add2
252 %add3 = add i16 %elt3, %add2
291 %cmp3 = icmp ult i16 %elt3, %min2
343 %cmp2 = icmp ult i16 %elt3, %min2
438 %cmp2 = icmp slt i16 %elt3, %min2
505 %cmp3 = icmp ugt i16 %elt3, %max2
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll30 %add3 = fadd fast half %elt3, %add2
72 %add3 = fadd fast half %elt3, %add2
142 %add3 = fadd fast half %elt3, %add2
180 %add3 = fsub fast half %elt3, %add2
210 %add3 = add i16 %elt3, %add2
252 %add3 = add i16 %elt3, %add2
291 %cmp3 = icmp ult i16 %elt3, %min2
343 %cmp2 = icmp ult i16 %elt3, %min2
438 %cmp2 = icmp slt i16 %elt3, %min2
505 %cmp3 = icmp ugt i16 %elt3, %max2
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Dreduction.ll30 %add3 = fadd fast half %elt3, %add2
72 %add3 = fadd fast half %elt3, %add2
142 %add3 = fadd fast half %elt3, %add2
180 %add3 = fsub fast half %elt3, %add2
210 %add3 = add i16 %elt3, %add2
252 %add3 = add i16 %elt3, %add2
291 %cmp3 = icmp ult i16 %elt3, %min2
343 %cmp2 = icmp ult i16 %elt3, %min2
438 %cmp2 = icmp slt i16 %elt3, %min2
505 %cmp3 = icmp ugt i16 %elt3, %max2
[all …]
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/lang/gcc48/gcc-4.8.5/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/lang/gnat_util/gcc-6-20180516/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \
/dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/sparc/
H A Dvec-init-3.inc23 #define V4QI_TEST(N, elt0, elt1, elt2, elt3) \
27 __v4qi v = { (elt0), (elt1), (elt2), (elt3) }; \
30 ((int)(elt2) << 8) | ((int)(elt3))); \
44 #define V8QI_TEST(N, elt0, elt1, elt2, elt3, elt4, elt5, elt6, elt7) \
49 __v8qi v = { (elt0), (elt1), (elt2), (elt3), \
54 ((long long)(elt3) << 32) | \

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