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/dports/lang/gnat_util/gcc-6-20180516/gcc/config/nds32/
H A Dnds32-doubleword.md62 /* reg <- const_int, we ask gcc to split instruction. */
160 output_asm_insn ("swi\t%0, [%2 + (%3)]", otherops);
161 output_asm_insn ("swi\t%1, [%2 + (%4)]", otherops);
165 output_asm_insn ("swi\t%1, [%2 + (%4)]", otherops);
166 output_asm_insn ("swi\t%0, [%2 + (%3)]", otherops);
173 output_asm_insn ("swi.gp\t%0, [ + %2]", otherops);
174 output_asm_insn ("swi.gp\t%1, [ + %2 + 4]", otherops);
202 Refer to gcc/emit-rtl.c for more information. */
214 ;; There is 'movd44' instruction for DImode/DFmode movement under V3/V3M ISA.
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/config/nds32/
H A Dnds32-doubleword.md62 /* reg <- const_int, we ask gcc to split instruction. */
160 output_asm_insn ("swi\t%0, [%2 + (%3)]", otherops);
161 output_asm_insn ("swi\t%1, [%2 + (%4)]", otherops);
165 output_asm_insn ("swi\t%1, [%2 + (%4)]", otherops);
166 output_asm_insn ("swi\t%0, [%2 + (%3)]", otherops);
173 output_asm_insn ("swi.gp\t%0, [ + %2]", otherops);
174 output_asm_insn ("swi.gp\t%1, [ + %2 + 4]", otherops);
202 Refer to gcc/emit-rtl.c for more information. */
214 ;; There is 'movd44' instruction for DImode/DFmode movement under V3/V3M ISA.
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/nds32/
H A Dnds32-doubleword.md62 /* reg <- const_int, we ask gcc to split instruction. */
160 output_asm_insn ("swi\t%0, [%2 + (%3)]", otherops);
161 output_asm_insn ("swi\t%1, [%2 + (%4)]", otherops);
165 output_asm_insn ("swi\t%1, [%2 + (%4)]", otherops);
166 output_asm_insn ("swi\t%0, [%2 + (%3)]", otherops);
173 output_asm_insn ("swi.gp\t%0, [ + %2]", otherops);
174 output_asm_insn ("swi.gp\t%1, [ + %2 + 4]", otherops);
202 Refer to gcc/emit-rtl.c for more information. */
214 ;; There is 'movd44' instruction for DImode/DFmode movement under V3/V3M ISA.
/dports/devel/binutils/binutils-2.37/cpu/
H A Depiphany.cpu32 ; - a 16/32 bit instruction machine (the default)
44 (comment "instruction is a 16 bit form")
52 (comment "instruction has a 3 bit immediate form")
60 (comment "instruction has a 8 bit immediate form")
135 ;; define the fields of the instruction.
188 (dnf f-trap-swi-9-1 "trap or swi" () 9 1)
1013 (duimmop swi_num "unsigned 6-bit swi#" h-uint f-trap-num)
1094 ;; Short (16 bit forms) must appear first so that instruction
2083 "swi $swi_num"
2100 (dni swi "software interrupt" (ALIAS SHORT-INSN UNCOND-CTI)
[all …]
H A Dmep-core.cpu2026 (dnci swi "software interrupt" (MAY_TRAP VOLATILE)
2027 "swi $uimm2"
3038 (emit sb rnc rma))
3042 (emit sh rns rma))
3046 (emit sw rnl rma))
3050 (emit lb rnc rma))
3054 (emit lh rns rma))
3058 (emit lw rnl rma))
3062 (emit lbu rnuc rma))
3066 (emit lhu rnus rma))
[all …]
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/cpu/
H A Depiphany.cpu32 ; - a 16/32 bit instruction machine (the default)
44 (comment "instruction is a 16 bit form")
52 (comment "instruction has a 3 bit immediate form")
60 (comment "instruction has a 8 bit immediate form")
135 ;; define the fields of the instruction.
188 (dnf f-trap-swi-9-1 "trap or swi" () 9 1)
1012 (duimmop swi_num "unsigned 6-bit swi#" h-uint f-trap-num)
1093 ;; Short (16 bit forms) must appear first so that instruction
2082 "swi $swi_num"
2099 (dni swi "software interrupt" (ALIAS SHORT-INSN UNCOND-CTI)
[all …]
H A Dmep-core.cpu2026 (dnci swi "software interrupt" (MAY_TRAP VOLATILE)
2027 "swi $uimm2"
3038 (emit sb rnc rma))
3042 (emit sh rns rma))
3046 (emit sw rnl rma))
3050 (emit lb rnc rma))
3054 (emit lh rns rma))
3058 (emit lw rnl rma))
3062 (emit lbu rnuc rma))
3066 (emit lhu rnus rma))
[all …]
/dports/devel/arm-elf-binutils/binutils-2.37/cpu/
H A Depiphany.cpu32 ; - a 16/32 bit instruction machine (the default)
44 (comment "instruction is a 16 bit form")
52 (comment "instruction has a 3 bit immediate form")
60 (comment "instruction has a 8 bit immediate form")
135 ;; define the fields of the instruction.
188 (dnf f-trap-swi-9-1 "trap or swi" () 9 1)
1013 (duimmop swi_num "unsigned 6-bit swi#" h-uint f-trap-num)
1094 ;; Short (16 bit forms) must appear first so that instruction
2083 "swi $swi_num"
2100 (dni swi "software interrupt" (ALIAS SHORT-INSN UNCOND-CTI)
[all …]
H A Dmep-core.cpu2026 (dnci swi "software interrupt" (MAY_TRAP VOLATILE)
2027 "swi $uimm2"
3038 (emit sb rnc rma))
3042 (emit sh rns rma))
3046 (emit sw rnl rma))
3050 (emit lb rnc rma))
3054 (emit lh rns rma))
3058 (emit lw rnl rma))
3062 (emit lbu rnuc rma))
3066 (emit lhu rnus rma))
[all …]
/dports/devel/gnulibiberty/binutils-2.37/cpu/
H A Depiphany.cpu32 ; - a 16/32 bit instruction machine (the default)
44 (comment "instruction is a 16 bit form")
52 (comment "instruction has a 3 bit immediate form")
60 (comment "instruction has a 8 bit immediate form")
135 ;; define the fields of the instruction.
188 (dnf f-trap-swi-9-1 "trap or swi" () 9 1)
1013 (duimmop swi_num "unsigned 6-bit swi#" h-uint f-trap-num)
1094 ;; Short (16 bit forms) must appear first so that instruction
2083 "swi $swi_num"
2100 (dni swi "software interrupt" (ALIAS SHORT-INSN UNCOND-CTI)
[all …]
H A Dmep-core.cpu2026 (dnci swi "software interrupt" (MAY_TRAP VOLATILE)
2027 "swi $uimm2"
3038 (emit sb rnc rma))
3042 (emit sh rns rma))
3046 (emit sw rnl rma))
3050 (emit lb rnc rma))
3054 (emit lh rns rma))
3058 (emit lw rnl rma))
3062 (emit lbu rnuc rma))
3066 (emit lhu rnus rma))
[all …]
/dports/lang/gnatdroid-binutils/binutils-2.27/cpu/
H A Depiphany.cpu32 ; - a 16/32 bit instruction machine (the default)
44 (comment "instruction is a 16 bit form")
52 (comment "instruction has a 3 bit immediate form")
60 (comment "instruction has a 8 bit immediate form")
135 ;; define the fields of the instruction.
188 (dnf f-trap-swi-9-1 "trap or swi" () 9 1)
1012 (duimmop swi_num "unsigned 6-bit swi#" h-uint f-trap-num)
1093 ;; Short (16 bit forms) must appear first so that instruction
2082 "swi $swi_num"
2099 (dni swi "software interrupt" (ALIAS SHORT-INSN UNCOND-CTI)
[all …]
H A Dmep-core.cpu2026 (dnci swi "software interrupt" (MAY_TRAP VOLATILE)
2027 "swi $uimm2"
3038 (emit sb rnc rma))
3042 (emit sh rns rma))
3046 (emit sw rnl rma))
3050 (emit lb rnc rma))
3054 (emit lh rns rma))
3058 (emit lw rnl rma))
3062 (emit lbu rnuc rma))
3066 (emit lhu rnus rma))
[all …]
/dports/devel/gdb/gdb-11.1/cpu/
H A Depiphany.cpu32 ; - a 16/32 bit instruction machine (the default)
44 (comment "instruction is a 16 bit form")
52 (comment "instruction has a 3 bit immediate form")
60 (comment "instruction has a 8 bit immediate form")
135 ;; define the fields of the instruction.
188 (dnf f-trap-swi-9-1 "trap or swi" () 9 1)
1013 (duimmop swi_num "unsigned 6-bit swi#" h-uint f-trap-num)
1094 ;; Short (16 bit forms) must appear first so that instruction
2083 "swi $swi_num"
2100 (dni swi "software interrupt" (ALIAS SHORT-INSN UNCOND-CTI)
[all …]
H A Dmep-core.cpu2026 (dnci swi "software interrupt" (MAY_TRAP VOLATILE)
2027 "swi $uimm2"
3038 (emit sb rnc rma))
3042 (emit sh rns rma))
3046 (emit sw rnl rma))
3050 (emit lb rnc rma))
3054 (emit lh rns rma))
3058 (emit lw rnl rma))
3062 (emit lbu rnuc rma))
3066 (emit lhu rnus rma))
[all …]
/dports/devel/gdb761/gdb-7.6.1/cpu/
H A Depiphany.cpu32 ; - a 16/32 bit instruction machine (the default)
44 (comment "instruction is a 16 bit form")
52 (comment "instruction has a 3 bit immediate form")
60 (comment "instruction has a 8 bit immediate form")
135 ;; define the fields of the instruction.
188 (dnf f-trap-swi-9-1 "trap or swi" () 9 1)
1012 (duimmop swi_num "unsigned 6-bit swi#" h-uint f-trap-num)
1093 ;; Short (16 bit forms) must appear first so that instruction
2082 "swi $swi_num"
2099 (dni swi "software interrupt" (ALIAS SHORT-INSN UNCOND-CTI)
[all …]
H A Dmep-core.cpu2026 (dnci swi "software interrupt" (MAY_TRAP VOLATILE)
2027 "swi $uimm2"
3038 (emit sb rnc rma))
3042 (emit sh rns rma))
3046 (emit sw rnl rma))
3050 (emit lb rnc rma))
3054 (emit lh rns rma))
3058 (emit lw rnl rma))
3062 (emit lbu rnuc rma))
3066 (emit lhu rnus rma))
[all …]
/dports/devel/asl/asl-current/tests/t_buf32/
H A Dt_buf32.asm11 ;* - added fill instruction.
1757 ;*Returns to monitor via an swi through swiin.
1785 SWIIN EQU * ; swi entry point
1806 ;* setbps - Replace user code with swi's at
1858 LDX PTR3 ; restore user swi vector
3163 ;* case P2INH: emit(PAGE2)
3168 ;* case INH: emit(baseop);
3615 ;*emit(baseop);
3622 ;*emit(lobyte);
3670 ;*if( a != PAGE1 ) emit(a);
[all …]
/dports/devel/avr-gdb/gdb-7.3.1/sim/testsuite/
H A DChangeLog181 successfully written. For error-case, emit strerror as well.
374 sim/arm/sub.cgs, sim/arm/swi.cgs, sim/arm/swp.cgs,
440 sim/arm/thumb/swi.cgs, sim/arm/thumb/tst.cgs: New files: Thumb
745 * sim/m32r/neg.cgs: Test NEG instruction.
746 * sim/m32r/not.cgs: Test NOT instruction.
754 * sim/m32r/or3.cgs: Test OR3 instruction.
756 * sim/m32r/rem.cgs: Test REM instruction.
757 * sim/m32r/sub.cgs: Test SUB instruction.
758 * sim/m32r/mv.cgs: Test MV instruction.
768 * sim/m32r/jl.cgs: Test JL instruction.
[all …]
/dports/lang/gnat_util/gcc-6-20180516/gcc/config/mep/
H A Dmep-core.cpu2024 (dnci swi "software interrupt" (MAY_TRAP VOLATILE)
2025 "swi $uimm2"
3036 (emit sb rnc rma))
3040 (emit sh rns rma))
3044 (emit sw rnl rma))
3048 (emit lb rnc rma))
3052 (emit lh rns rma))
3056 (emit lw rnl rma))
3060 (emit lbu rnuc rma))
3064 (emit lhu rnus rma))
[all …]
/dports/lang/gcc48/gcc-4.8.5/gcc/config/mep/
H A Dmep-core.cpu2024 (dnci swi "software interrupt" (MAY_TRAP VOLATILE)
2025 "swi $uimm2"
3036 (emit sb rnc rma))
3040 (emit sh rns rma))
3044 (emit sw rnl rma))
3048 (emit lb rnc rma))
3052 (emit lh rns rma))
3056 (emit lw rnl rma))
3060 (emit lbu rnuc rma))
3064 (emit lhu rnus rma))
[all …]
/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/config/mep/
H A Dmep-core.cpu2024 (dnci swi "software interrupt" (MAY_TRAP VOLATILE)
2025 "swi $uimm2"
3036 (emit sb rnc rma))
3040 (emit sh rns rma))
3044 (emit sw rnl rma))
3048 (emit lb rnc rma))
3052 (emit lh rns rma))
3056 (emit lw rnl rma))
3060 (emit lbu rnuc rma))
3064 (emit lhu rnus rma))
[all …]
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/config/mep/
H A Dmep-core.cpu2024 (dnci swi "software interrupt" (MAY_TRAP VOLATILE)
2025 "swi $uimm2"
3036 (emit sb rnc rma))
3040 (emit sh rns rma))
3044 (emit sw rnl rma))
3048 (emit lb rnc rma))
3052 (emit lh rns rma))
3056 (emit lw rnl rma))
3060 (emit lbu rnuc rma))
3064 (emit lhu rnus rma))
[all …]
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/mep/
H A Dmep-core.cpu2024 (dnci swi "software interrupt" (MAY_TRAP VOLATILE)
2025 "swi $uimm2"
3036 (emit sb rnc rma))
3040 (emit sh rns rma))
3044 (emit sw rnl rma))
3048 (emit lb rnc rma))
3052 (emit lh rns rma))
3056 (emit lw rnl rma))
3060 (emit lbu rnuc rma))
3064 (emit lhu rnus rma))
[all …]
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/gas/doc/
H A Das.info-1998 This passes two options to the assembler: `-alh' (emit a listing to
3323 such assemblers, but does not actually emit anything for it.
3435 For each expression, emit a number that, at run time, is the value of
5376 Software interrupt (swi) instruction.
6107 When `-N' is specified, `as' will emit a warning when a 16-bit
6781 instructions can be done in parallel), and if so, emit them as
7099 Recognize and emit additional instructions for the H8/300H
7100 variant, and also make `.int' emit 32-bit numbers rather than the
7110 in normal mode, and also make `.int' emit 32-bit numbers rather
7114 Recognize and emit additional instructions for the H8S variant in
[all …]

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