| /dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/lang/gcc9-devel/gcc-9-20211007/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/devel/riscv64-gcc/gcc-8.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/lang/gcc9/gcc-9.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/lang/gcc10-devel/gcc-10-20211008/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
11 VECT_VAR_DECL(expected_positive, hfloat, 16, 4) [] = { 0x3834, 0x3834, variable
13 VECT_VAR_DECL(expected_positive, hfloat, 16, 8) [] = { 0x2018, 0x2018, variable
19 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
136 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
137 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
139 CHECK_FP(TEST_MSG, float, 16, 4, PRIx16, expected_positive, CMT); in exec_vrecpe()
140 CHECK_FP(TEST_MSG, float, 16, 8, PRIx16, expected_positive, CMT); in exec_vrecpe()
142 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
[all …]
|
| /dports/lang/gcc6-aux/gcc-6-20180516/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
10 VECT_VAR_DECL(expected_positive,hfloat,32,2) [] = { 0x3f068000, 0x3f068000 }; variable
11 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
76 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
77 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
78 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
79 CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
|
| /dports/lang/gnat_util/gcc-6-20180516/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vrecpe.c | 7 VECT_VAR_DECL(expected_positive,uint,32,2) [] = { 0xffffffff, 0xffffffff }; variable
8 VECT_VAR_DECL(expected_positive,uint,32,4) [] = { 0xbf000000, 0xbf000000, variable
10 VECT_VAR_DECL(expected_positive,hfloat,32,2) [] = { 0x3f068000, 0x3f068000 }; variable
11 VECT_VAR_DECL(expected_positive,hfloat,32,4) [] = { 0x3c030000, 0x3c030000, variable
76 CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
77 CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
78 CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected_positive, CMT); in exec_vrecpe()
79 CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected_positive, CMT); in exec_vrecpe()
|