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Searched refs:expectedfma2 (Results 1 – 16 of 16) sorted by relevance

/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
/dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
/dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
/dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
/dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
/dports/lang/gcc9/gcc-9.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/
H A Dvfms_vfma_n.c69 VECT_VAR_DECL(expectedfma2, float, 32, 2) [] = {A4 + B4 * E2, A5 + B5 * E2}; variable
85 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 2);
102 VECT_VAR_DECL(expectedfma2, float, 32, 4) [] = {A0 + B0 * E2, A2 + B2 * E2, variable
120 (hfloat32_t *) VECT_VAR (expectedfma2, float, 32, 4);
136 VECT_VAR_DECL(expectedfma2, float, 64, 2) [] = {DA4 + DB4 * DE2, variable
153 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 2);
163 VECT_VAR_DECL(expectedfma2, float, 64, 1) [] = {DA4 + DB4 * DE2}; variable
179 (hfloat64_t *) VECT_VAR (expectedfma2, float, 64, 1);