| /dports/cad/yosys/yosys-yosys-0.12/kernel/ |
| H A D | calc.cc | 29 static void extend_u0(RTLIL::Const &arg, int width, bool is_signed) in extend_u0() function
138 extend_u0(arg1_ext, result_len, signed1); in const_not()
159 extend_u0(arg1, result_len, signed1); in logic_wrapper()
160 extend_u0(arg2, result_len, signed2); in logic_wrapper()
311 extend_u0(arg1_ext, result_len, signed1); in const_shl()
318 extend_u0(arg1_ext, max(result_len, GetSize(arg1)), signed1); in const_shr()
373 extend_u0(arg1_ext, width, signed1 && signed2); in const_eq()
374 extend_u0(arg2_ext, width, signed1 && signed2); in const_eq()
407 extend_u0(arg1_ext, width, signed1 && signed2); in const_eqx()
408 extend_u0(arg2_ext, width, signed1 && signed2); in const_eqx()
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| H A D | consteval.h | 254 sig_a.extend_u0(GetSize(sig_y), signed_a); in eval()
255 sig_b.extend_u0(GetSize(sig_y), signed_b); in eval()
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| /dports/cad/yosys/yosys-yosys-0.12/passes/opt/ |
| H A D | opt_mem_priority.cc | 72 addr1.extend_u0(abits); in execute()
73 addr2.extend_u0(abits); in execute()
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| H A D | share.cc | 201 sig_a1.extend_u0(GetSize(sig_a), p1.is_signed); in share_macc_ports()
539 a1.extend_u0(a_width, a_signed); in make_supercell()
540 a2.extend_u0(a_width, a_signed); in make_supercell()
645 a1.extend_u0(a_width, false); in make_supercell()
646 a2.extend_u0(a_width, false); in make_supercell()
650 a1.extend_u0(a_width, a_signed); in make_supercell()
651 a2.extend_u0(a_width, a_signed); in make_supercell()
654 b1.extend_u0(b_width, b_signed); in make_supercell()
655 b2.extend_u0(b_width, b_signed); in make_supercell()
715 addr1.extend_u0(GetSize(addr2)); in make_supercell()
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| H A D | pmux2shiftx.cc | 298 A.extend_u0(b_width, a_signed); in execute()
303 B.extend_u0(a_width, b_signed); in execute()
784 A.extend_u0(b_width, a_signed); in execute()
789 B.extend_u0(a_width, b_signed); in execute()
841 sig.extend_u0(GetSize(Y)); in execute()
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| H A D | opt_expr.cc | 123 out_val.extend_u0(Y.size(), false); in replace_cell()
146 sig_a.extend_u0(sig_y.size(), a_signed); in group_cell_inputs()
147 sig_b.extend_u0(sig_y.size(), b_signed); in group_cell_inputs()
1064 …a.extend_u0(width, cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_b… in replace_const_cells()
1075 new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false); in replace_const_cells()
1088 new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false); in replace_const_cells()
1167 sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool()); in replace_const_cells()
1268 a.extend_u0(y_width, is_signed); in replace_const_cells()
1274 ab.extend_u0(y_width, is_signed); in replace_const_cells()
1719 sig_a.extend_u0(GetSize(sig_y), is_signed); in replace_const_cells()
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| H A D | opt_share.cc | 194 operand.sig.extend_u0(max_width, operand.is_signed); in merge_operators()
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| /dports/cad/yosys/yosys-yosys-0.12/passes/pmgen/ |
| H A D | xilinx_dsp.cc | 112 A.extend_u0(12, lane->getParam(ID::A_SIGNED).as_bool()); in xilinx_simd_pack()
113 B.extend_u0(12, lane->getParam(ID::B_SIGNED).as_bool()); in xilinx_simd_pack()
200 A.extend_u0(24, lane->getParam(ID::A_SIGNED).as_bool()); in xilinx_simd_pack()
201 B.extend_u0(24, lane->getParam(ID::B_SIGNED).as_bool()); in xilinx_simd_pack()
287 st.sigA.extend_u0(30, A_SIGNED); in xilinx_dsp_pack()
288 st.sigD.extend_u0(25, D_SIGNED); in xilinx_dsp_pack()
326 st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool()); in xilinx_dsp_pack()
328 st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool()); in xilinx_dsp_pack()
511 st.sigB.extend_u0(18, B_SIGNED); in xilinx_dsp48a_pack()
512 st.sigD.extend_u0(18, D_SIGNED); in xilinx_dsp48a_pack()
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| H A D | peepopt_muldiv.pmg | 32 val_y.extend_u0(GetSize(div_y), param(div, \A_SIGNED).as_bool());
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| H A D | ice40_dsp.cc | 76 A.extend_u0(16, st.mul->getParam(ID::A_SIGNED).as_bool()); in create_ice40_dsp()
80 B.extend_u0(16, st.mul->getParam(ID::B_SIGNED).as_bool()); in create_ice40_dsp()
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| H A D | ice40_dsp.pmg | 307 sigCD.extend_u0(32, cd_signed);
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| /dports/cad/yosys/yosys-yosys-0.12/passes/techmap/ |
| H A D | simplemap.cc | 35 sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); in simplemap_not()
50 sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); in simplemap_pos()
61 sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); in simplemap_bitop()
62 sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool()); in simplemap_bitop()
306 lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int()); in simplemap_lut()
332 table.extend_u0(2 * width * depth); in simplemap_sop()
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| H A D | maccmap.cc | 52 a.extend_u0(width, is_signed); in add()
68 a.extend_u0(width, is_signed); in add()
71 b.extend_u0(width, is_signed); in add()
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| H A D | flatten.cc | 212 new_conn.second.extend_u0(new_conn.first.size(), is_signed); in flatten_cell()
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| H A D | alumacc.cc | 522 sig.extend_u0(GetSize(cmp_y)); in replace_alu()
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| /dports/cad/yosys/yosys-yosys-0.12/passes/memory/ |
| H A D | memory_memx.cc | 43 addr.extend_u0(32); in make_addr_check()
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| H A D | memory_share.cc | 415 last_addr.extend_u0(GetSize(this_addr)); in consolidate_wr_using_sat()
417 this_addr.extend_u0(GetSize(last_addr)); in consolidate_wr_using_sat()
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| H A D | memory_dff.cc | 91 raddr.extend_u0(abits); in addr_eq()
92 waddr.extend_u0(abits); in addr_eq()
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| H A D | memory_map.cc | 235 rd_addr.extend_u0(abits, false); in handle_memory()
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| /dports/cad/yosys/yosys-yosys-0.12/frontends/ast/ |
| H A D | genrtlil.cc | 76 sig.extend_u0(width, is_signed); in widthExtend()
1520 sig.extend_u0(width_hint, sign_hint); in genRTLIL()
1534 sig.extend_u0(width, sign_hint); in genRTLIL()
1545 sig.extend_u0(width_hint, false); in genRTLIL()
1560 sig.extend_u0(width_hint, false); in genRTLIL()
1757 sig.extend_u0(width_hint, sign_hint); in genRTLIL()
2126 sig.extend_u0(width, is_signed); in genWidthRTLIL()
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| /dports/cad/yosys/yosys-yosys-0.12/passes/fsm/ |
| H A D | fsm_extract.cc | 43 sig.extend_u0(dff_out.size(), false); in find_states()
102 new_reset_state.extend_u0(GetSize(*reset_state)); in find_states()
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| /dports/cad/yosys/yosys-yosys-0.12/backends/spice/ |
| H A D | spice.cc | 106 sig.extend_u0(wire->width, false); in print_spice_module()
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| /dports/cad/yosys/yosys-yosys-0.12/backends/smt2/ |
| H A D | smt2.cc | 454 sig_a.extend_u0(width, is_signed); in export_bvop()
459 sig_b.extend_u0(width, is_signed && !(type == 's')); in export_bvop()
742 addr_sig.extend_u0(abits); in export_cell()
786 addr_sig.extend_u0(abits); in export_cell()
1118 addr_sig.extend_u0(abits); in run()
1165 addr_sig.extend_u0(abits); in run()
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| /dports/cad/yosys/yosys-yosys-0.12/passes/proc/ |
| H A D | proc_arst.cc | 308 value.extend_u0(chunk.wire->width, false); in execute()
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| /dports/cad/yosys/yosys-yosys-0.12/backends/btor/ |
| H A D | btor.cc | 804 wa.extend_u0(abits); in export_cell()
841 ra.extend_u0(abits); in export_cell()
1268 wa.extend_u0(abits); in BtorWorker()
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