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/dports/emulators/qemu-utils/qemu-4.2.1/target/riscv/
H A Dinstmap.h300 #define GET_B_IMM(inst) ((extract32(inst, 8, 4) << 1) \
301 | (extract32(inst, 25, 6) << 5) \
302 | (extract32(inst, 7, 1) << 11) \
305 #define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \
313 #define GET_RM(inst) extract32(inst, 12, 3)
314 #define GET_RS3(inst) extract32(inst, 27, 5)
315 #define GET_RS1(inst) extract32(inst, 15, 5)
316 #define GET_RS2(inst) extract32(inst, 20, 5)
317 #define GET_RD(inst) extract32(inst, 7, 5)
362 #define GET_C_SIMM3(inst) extract32(inst, 10, 3)
[all …]
/dports/emulators/qemu42/qemu-4.2.1/target/riscv/
H A Dinstmap.h300 #define GET_B_IMM(inst) ((extract32(inst, 8, 4) << 1) \
301 | (extract32(inst, 25, 6) << 5) \
302 | (extract32(inst, 7, 1) << 11) \
305 #define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \
313 #define GET_RM(inst) extract32(inst, 12, 3)
314 #define GET_RS3(inst) extract32(inst, 27, 5)
315 #define GET_RS1(inst) extract32(inst, 15, 5)
316 #define GET_RS2(inst) extract32(inst, 20, 5)
317 #define GET_RD(inst) extract32(inst, 7, 5)
362 #define GET_C_SIMM3(inst) extract32(inst, 10, 3)
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/riscv/
H A Dinstmap.h297 #define GET_B_IMM(inst) ((extract32(inst, 8, 4) << 1) \
298 | (extract32(inst, 25, 6) << 5) \
299 | (extract32(inst, 7, 1) << 11) \
302 #define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \
310 #define GET_RM(inst) extract32(inst, 12, 3)
311 #define GET_RS3(inst) extract32(inst, 27, 5)
312 #define GET_RS1(inst) extract32(inst, 15, 5)
313 #define GET_RS2(inst) extract32(inst, 20, 5)
314 #define GET_RD(inst) extract32(inst, 7, 5)
359 #define GET_C_SIMM3(inst) extract32(inst, 10, 3)
[all …]
/dports/emulators/qemu5/qemu-5.2.0/target/riscv/
H A Dinstmap.h300 #define GET_B_IMM(inst) ((extract32(inst, 8, 4) << 1) \
301 | (extract32(inst, 25, 6) << 5) \
302 | (extract32(inst, 7, 1) << 11) \
305 #define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \
313 #define GET_RM(inst) extract32(inst, 12, 3)
314 #define GET_RS3(inst) extract32(inst, 27, 5)
315 #define GET_RS1(inst) extract32(inst, 15, 5)
316 #define GET_RS2(inst) extract32(inst, 20, 5)
317 #define GET_RD(inst) extract32(inst, 7, 5)
362 #define GET_C_SIMM3(inst) extract32(inst, 10, 3)
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/riscv/
H A Dinstmap.h300 #define GET_B_IMM(inst) ((extract32(inst, 8, 4) << 1) \
301 | (extract32(inst, 25, 6) << 5) \
302 | (extract32(inst, 7, 1) << 11) \
305 #define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \
313 #define GET_RM(inst) extract32(inst, 12, 3)
314 #define GET_RS3(inst) extract32(inst, 27, 5)
315 #define GET_RS1(inst) extract32(inst, 15, 5)
316 #define GET_RS2(inst) extract32(inst, 20, 5)
317 #define GET_RD(inst) extract32(inst, 7, 5)
362 #define GET_C_SIMM3(inst) extract32(inst, 10, 3)
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/riscv/
H A Dinstmap.h300 #define GET_B_IMM(inst) ((extract32(inst, 8, 4) << 1) \
301 | (extract32(inst, 25, 6) << 5) \
302 | (extract32(inst, 7, 1) << 11) \
305 #define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \
313 #define GET_RM(inst) extract32(inst, 12, 3)
314 #define GET_RS3(inst) extract32(inst, 27, 5)
315 #define GET_RS1(inst) extract32(inst, 15, 5)
316 #define GET_RS2(inst) extract32(inst, 20, 5)
317 #define GET_RD(inst) extract32(inst, 7, 5)
362 #define GET_C_SIMM3(inst) extract32(inst, 10, 3)
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/
H A Dinstmap.h300 #define GET_B_IMM(inst) ((extract32(inst, 8, 4) << 1) \
301 | (extract32(inst, 25, 6) << 5) \
302 | (extract32(inst, 7, 1) << 11) \
305 #define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \
313 #define GET_RM(inst) extract32(inst, 12, 3)
314 #define GET_RS3(inst) extract32(inst, 27, 5)
315 #define GET_RS1(inst) extract32(inst, 15, 5)
316 #define GET_RS2(inst) extract32(inst, 20, 5)
317 #define GET_RD(inst) extract32(inst, 7, 5)
362 #define GET_C_SIMM3(inst) extract32(inst, 10, 3)
[all …]
/dports/emulators/qemu/qemu-6.2.0/target/riscv/
H A Dinstmap.h300 #define GET_B_IMM(inst) ((extract32(inst, 8, 4) << 1) \
301 | (extract32(inst, 25, 6) << 5) \
302 | (extract32(inst, 7, 1) << 11) \
305 #define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \
313 #define GET_RM(inst) extract32(inst, 12, 3)
314 #define GET_RS3(inst) extract32(inst, 27, 5)
315 #define GET_RS1(inst) extract32(inst, 15, 5)
316 #define GET_RS2(inst) extract32(inst, 20, 5)
317 #define GET_RD(inst) extract32(inst, 7, 5)
362 #define GET_C_SIMM3(inst) extract32(inst, 10, 3)
[all …]
/dports/emulators/qemu60/qemu-6.0.0/target/riscv/
H A Dinstmap.h300 #define GET_B_IMM(inst) ((extract32(inst, 8, 4) << 1) \
301 | (extract32(inst, 25, 6) << 5) \
302 | (extract32(inst, 7, 1) << 11) \
305 #define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \
313 #define GET_RM(inst) extract32(inst, 12, 3)
314 #define GET_RS3(inst) extract32(inst, 27, 5)
315 #define GET_RS1(inst) extract32(inst, 15, 5)
316 #define GET_RS2(inst) extract32(inst, 20, 5)
317 #define GET_RD(inst) extract32(inst, 7, 5)
362 #define GET_C_SIMM3(inst) extract32(inst, 10, 3)
[all …]
/dports/emulators/qemu/qemu-6.2.0/hw/arm/
H A Dsmmuv3-internal.h501 #define STE_VALID(x) extract32((x)->word[0], 0, 1)
503 #define STE_CONFIG(x) extract32((x)->word[0], 1, 3)
573 #define CD_VALID(x) extract32((x)->word[0], 31, 1)
574 #define CD_ASID(x) extract32((x)->word[1], 16, 16)
588 #define CD_ENDI(x) extract32((x)->word[0], 15, 1)
589 #define CD_IPS(x) extract32((x)->word[1], 0 , 3)
590 #define CD_TBI(x) extract32((x)->word[1], 6 , 2)
593 #define CD_S(x) extract32((x)->word[1], 12, 1)
594 #define CD_R(x) extract32((x)->word[1], 13, 1)
595 #define CD_A(x) extract32((x)->word[1], 14, 1)
[all …]
/dports/emulators/qemu60/qemu-6.0.0/hw/arm/
H A Dsmmuv3-internal.h501 #define STE_VALID(x) extract32((x)->word[0], 0, 1)
503 #define STE_CONFIG(x) extract32((x)->word[0], 1, 3)
573 #define CD_VALID(x) extract32((x)->word[0], 30, 1)
574 #define CD_ASID(x) extract32((x)->word[1], 16, 16)
588 #define CD_ENDI(x) extract32((x)->word[0], 15, 1)
589 #define CD_IPS(x) extract32((x)->word[1], 0 , 3)
590 #define CD_TBI(x) extract32((x)->word[1], 6 , 2)
593 #define CD_S(x) extract32((x)->word[1], 12, 1)
594 #define CD_R(x) extract32((x)->word[1], 13, 1)
595 #define CD_A(x) extract32((x)->word[1], 14, 1)
[all …]
/dports/emulators/qemu5/qemu-5.2.0/hw/arm/
H A Dsmmuv3-internal.h501 #define STE_VALID(x) extract32((x)->word[0], 0, 1)
503 #define STE_CONFIG(x) extract32((x)->word[0], 1, 3)
573 #define CD_VALID(x) extract32((x)->word[0], 30, 1)
574 #define CD_ASID(x) extract32((x)->word[1], 16, 16)
588 #define CD_ENDI(x) extract32((x)->word[0], 15, 1)
589 #define CD_IPS(x) extract32((x)->word[1], 0 , 3)
590 #define CD_TBI(x) extract32((x)->word[1], 6 , 2)
593 #define CD_S(x) extract32((x)->word[1], 12, 1)
594 #define CD_R(x) extract32((x)->word[1], 13, 1)
595 #define CD_A(x) extract32((x)->word[1], 14, 1)
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/arm/
H A Dsmmuv3-internal.h501 #define STE_VALID(x) extract32((x)->word[0], 0, 1)
503 #define STE_CONFIG(x) extract32((x)->word[0], 1, 3)
573 #define CD_VALID(x) extract32((x)->word[0], 31, 1)
574 #define CD_ASID(x) extract32((x)->word[1], 16, 16)
588 #define CD_ENDI(x) extract32((x)->word[0], 15, 1)
589 #define CD_IPS(x) extract32((x)->word[1], 0 , 3)
590 #define CD_TBI(x) extract32((x)->word[1], 6 , 2)
593 #define CD_S(x) extract32((x)->word[1], 12, 1)
594 #define CD_R(x) extract32((x)->word[1], 13, 1)
595 #define CD_A(x) extract32((x)->word[1], 14, 1)
[all …]
/dports/emulators/qemu42/qemu-4.2.1/hw/arm/
H A Dsmmuv3-internal.h494 #define STE_VALID(x) extract32((x)->word[0], 0, 1)
496 #define STE_CONFIG(x) extract32((x)->word[0], 1, 3)
566 #define CD_VALID(x) extract32((x)->word[0], 30, 1)
567 #define CD_ASID(x) extract32((x)->word[1], 16, 16)
580 #define CD_ENDI(x) extract32((x)->word[0], 15, 1)
581 #define CD_IPS(x) extract32((x)->word[1], 0 , 3)
582 #define CD_TBI(x) extract32((x)->word[1], 6 , 2)
585 #define CD_S(x) extract32((x)->word[1], 12, 1)
586 #define CD_R(x) extract32((x)->word[1], 13, 1)
587 #define CD_A(x) extract32((x)->word[1], 14, 1)
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/hw/arm/
H A Dsmmuv3-internal.h494 #define STE_VALID(x) extract32((x)->word[0], 0, 1)
496 #define STE_CONFIG(x) extract32((x)->word[0], 1, 3)
566 #define CD_VALID(x) extract32((x)->word[0], 30, 1)
567 #define CD_ASID(x) extract32((x)->word[1], 16, 16)
580 #define CD_ENDI(x) extract32((x)->word[0], 15, 1)
581 #define CD_IPS(x) extract32((x)->word[1], 0 , 3)
582 #define CD_TBI(x) extract32((x)->word[1], 6 , 2)
585 #define CD_S(x) extract32((x)->word[1], 12, 1)
586 #define CD_R(x) extract32((x)->word[1], 13, 1)
587 #define CD_A(x) extract32((x)->word[1], 14, 1)
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/arm/
H A Dsmmuv3-internal.h493 #define STE_VALID(x) extract32((x)->word[0], 0, 1)
495 #define STE_CONFIG(x) extract32((x)->word[0], 1, 3)
565 #define CD_VALID(x) extract32((x)->word[0], 30, 1)
566 #define CD_ASID(x) extract32((x)->word[1], 16, 16)
579 #define CD_ENDI(x) extract32((x)->word[0], 15, 1)
580 #define CD_IPS(x) extract32((x)->word[1], 0 , 3)
581 #define CD_TBI(x) extract32((x)->word[1], 6 , 2)
584 #define CD_S(x) extract32((x)->word[1], 12, 1)
585 #define CD_R(x) extract32((x)->word[1], 13, 1)
586 #define CD_A(x) extract32((x)->word[1], 14, 1)
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/arm/
H A Dsmmuv3-internal.h494 #define STE_VALID(x) extract32((x)->word[0], 0, 1)
496 #define STE_CONFIG(x) extract32((x)->word[0], 1, 3)
566 #define CD_VALID(x) extract32((x)->word[0], 30, 1)
567 #define CD_ASID(x) extract32((x)->word[1], 16, 16)
580 #define CD_ENDI(x) extract32((x)->word[0], 15, 1)
581 #define CD_IPS(x) extract32((x)->word[1], 0 , 3)
582 #define CD_TBI(x) extract32((x)->word[1], 6 , 2)
585 #define CD_S(x) extract32((x)->word[1], 12, 1)
586 #define CD_R(x) extract32((x)->word[1], 13, 1)
587 #define CD_A(x) extract32((x)->word[1], 14, 1)
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/arm/
H A Dsmmuv3-internal.h494 #define STE_VALID(x) extract32((x)->word[0], 0, 1)
496 #define STE_CONFIG(x) extract32((x)->word[0], 1, 3)
566 #define CD_VALID(x) extract32((x)->word[0], 30, 1)
567 #define CD_ASID(x) extract32((x)->word[1], 16, 16)
580 #define CD_ENDI(x) extract32((x)->word[0], 15, 1)
581 #define CD_IPS(x) extract32((x)->word[1], 0 , 3)
582 #define CD_TBI(x) extract32((x)->word[1], 6 , 2)
585 #define CD_S(x) extract32((x)->word[1], 12, 1)
586 #define CD_R(x) extract32((x)->word[1], 13, 1)
587 #define CD_A(x) extract32((x)->word[1], 14, 1)
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/hppa/
H A Dtranslate.c805 unsigned r1 = extract32(insn, 6, 1); in assemble_rt64()
806 unsigned r0 = extract32(insn, 0, 5); in assemble_rt64()
812 unsigned r1 = extract32(insn, 7, 1); in assemble_ra64()
826 unsigned r2 = extract32(insn, 8, 1); in assemble_rc64()
828 unsigned r0 = extract32(insn, 9, 2); in assemble_rc64()
2411 sp = extract32(insn, 14, 2); in trans_ixtlbx()
2436 unsigned m = extract32(insn, 5, 1); in trans_pxtlbx()
2446 sp = extract32(insn, 14, 2); in trans_pxtlbx()
2473 unsigned m = extract32(insn, 5, 1); in trans_lpa()
2946 unsigned m = extract32(insn, 5, 1); in trans_ld_idx_i()
[all …]
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/mips/tcg/
H A Dmxu_translate.c507 XRa = extract32(ctx->opcode, 6, 5); in gen_mxu_s32i2m()
508 Rb = extract32(ctx->opcode, 16, 5); in gen_mxu_s32i2m()
530 XRa = extract32(ctx->opcode, 6, 5); in gen_mxu_s32m2i()
531 Rb = extract32(ctx->opcode, 16, 5); in gen_mxu_s32m2i()
555 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s8ldd()
556 s8 = extract32(ctx->opcode, 10, 8); in gen_mxu_s8ldd()
558 Rb = extract32(ctx->opcode, 21, 5); in gen_mxu_s8ldd()
634 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d16mul()
688 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d16mac()
769 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_q8mul_q8mulsu()
[all …]
/dports/emulators/qemu/qemu-6.2.0/target/mips/tcg/
H A Dmxu_translate.c507 XRa = extract32(ctx->opcode, 6, 5); in gen_mxu_s32i2m()
508 Rb = extract32(ctx->opcode, 16, 5); in gen_mxu_s32i2m()
530 XRa = extract32(ctx->opcode, 6, 5); in gen_mxu_s32m2i()
531 Rb = extract32(ctx->opcode, 16, 5); in gen_mxu_s32m2i()
555 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s8ldd()
556 s8 = extract32(ctx->opcode, 10, 8); in gen_mxu_s8ldd()
558 Rb = extract32(ctx->opcode, 21, 5); in gen_mxu_s8ldd()
634 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d16mul()
688 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d16mac()
769 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_q8mul_q8mulsu()
[all …]
/dports/emulators/qemu60/qemu-6.0.0/target/mips/
H A Dmxu_translate.c507 XRa = extract32(ctx->opcode, 6, 5); in gen_mxu_s32i2m()
508 Rb = extract32(ctx->opcode, 16, 5); in gen_mxu_s32i2m()
530 XRa = extract32(ctx->opcode, 6, 5); in gen_mxu_s32m2i()
531 Rb = extract32(ctx->opcode, 16, 5); in gen_mxu_s32m2i()
555 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_s8ldd()
556 s8 = extract32(ctx->opcode, 10, 8); in gen_mxu_s8ldd()
558 Rb = extract32(ctx->opcode, 21, 5); in gen_mxu_s8ldd()
634 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d16mul()
688 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_d16mac()
769 XRa = extract32(ctx->opcode, 6, 4); in gen_mxu_q8mul_q8mulsu()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/
H A Dtranslate-a64.c1287 rt = extract32(insn, 0, 5); in disas_comp_b_imm()
1315 bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); in disas_test_b_imm()
1318 rt = extract32(insn, 0, 5); in disas_test_b_imm()
3280 offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); in disas_ldst_pac()
3453 if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { in disas_ldst_multiple_struct()
4839 if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { in disas_cond_select()
7698 uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); in disas_simd_mod_imm()
10064 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); in disas_simd_scalar_two_reg_misc()
12237 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); in disas_simd_two_reg_misc()
12296 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); in disas_simd_two_reg_misc()
[all …]
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/
H A Dtranslate-a64.c1287 rt = extract32(insn, 0, 5); in disas_comp_b_imm()
1315 bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); in disas_test_b_imm()
1318 rt = extract32(insn, 0, 5); in disas_test_b_imm()
3280 offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); in disas_ldst_pac()
3453 if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { in disas_ldst_multiple_struct()
4839 if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { in disas_cond_select()
7697 uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); in disas_simd_mod_imm()
10063 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); in disas_simd_scalar_two_reg_misc()
12233 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); in disas_simd_two_reg_misc()
12292 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); in disas_simd_two_reg_misc()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/target/arm/
H A Dtranslate-a64.c1263 rt = extract32(insn, 0, 5); in disas_comp_b_imm()
1291 bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); in disas_test_b_imm()
1294 rt = extract32(insn, 0, 5); in disas_test_b_imm()
3204 offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); in disas_ldst_pac()
3295 if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { in disas_ldst_multiple_struct()
4673 if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) { in disas_cond_select()
7522 uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5); in disas_simd_mod_imm()
9888 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); in disas_simd_scalar_two_reg_misc()
12081 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); in disas_simd_two_reg_misc()
12140 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1); in disas_simd_two_reg_misc()
[all …]

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