| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/gpmc/ |
| H A D | gpmc.v | 34 input fifo_clk, input fifo_rst, port
63 .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
68 (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
73 .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
88 .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
94 (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
99 (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
117 .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), .arst(fifo_rst | arst),
122 (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
148 (.clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
[all …]
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/gpif/ |
| H A D | gpif.v | 79 .sys_clk(fifo_clk), .sys_rst(fifo_rst),
89 (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
94 (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
99 (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
115 (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
120 (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
125 (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
136 .sys_clk(fifo_clk), .sys_rst(fifo_rst),
145 (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
157 (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
[all …]
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| H A D | slave_fifo.v | 41 input fifo_clk, input fifo_rst, port
238 .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
246 .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
259 .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
267 .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
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| H A D | gpmc16_to_fifo36.v | 33 input fifo_clk, input fifo_rst, port
62 .arst(fifo_rst | gpif_rst));
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| H A D | fifo36_to_gpmc16.v | 27 input fifo_clk, input fifo_rst, port
52 .arst(fifo_rst | gpif_rst));
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/gpif2/ |
| H A D | gpif2_slave_fifo32.v | 42 input fifo_rst, port
485 .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
495 .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
508 .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
518 .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
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| H A D | gpif2_to_fifo64.v | 27 input fifo_rst, port
82 .reset(fifo_rst | gpif_rst),
98 .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
114 .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
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| H A D | fifo64_to_gpif2.v | 16 input fifo_clk, input fifo_rst, port
36 .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0),
47 .reset(fifo_rst | gpif_rst),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/top/B100/ |
| H A D | B100.v | 207 .fifo_clk(clk_fpga), .fifo_rst(reset),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/ |
| H A D | b205.v | 289 .fifo_clk(bus_clk), .fifo_rst(bus_rst),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/ |
| H A D | b200.v | 351 .fifo_clk(bus_clk), .fifo_rst(bus_rst),
|