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/dports/emulators/qemu60/qemu-6.0.0/target/hexagon/
H A Dconv_emu.c80 static uint32_t conv_df_to_4u_n(float64 fp64, int will_negate, in conv_df_to_4u_n() argument
84 tmp = conv_f64_to_8u_n(fp64, will_negate, fp_status); in conv_df_to_4u_n()
157 float64 fp64 = float32_to_float64(in, fp_status); in conv_sf_to_8u() local
158 return conv_df_to_8u(fp64, fp_status); in conv_sf_to_8u()
163 float64 fp64 = float32_to_float64(in, fp_status); in conv_sf_to_4u() local
164 return conv_df_to_4u(fp64, fp_status); in conv_sf_to_4u()
169 float64 fp64 = float32_to_float64(in, fp_status); in conv_sf_to_8s() local
170 return conv_df_to_8s(fp64, fp_status); in conv_sf_to_8s()
175 float64 fp64 = float32_to_float64(in, fp_status); in conv_sf_to_4s() local
176 return conv_df_to_4s(fp64, fp_status); in conv_sf_to_4s()
/dports/lang/go-devel/go-becaeea1199b875bc24800fa88f2f4fea119bf78/src/cmd/compile/internal/ssa/gen/
H A DWasmOps.go95 fp64 = buildReg("F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31")
100 callerSave = gp | fp32 | fp64 | buildReg("g")
113 fp64_01 = regInfo{inputs: nil, outputs: []regMask{fp64}}
114 fp64_11 = regInfo{inputs: []regMask{fp64}, outputs: []regMask{fp64}}
115 fp64_21 = regInfo{inputs: []regMask{fp64, fp64}, outputs: []regMask{fp64}}
116 fp64_21gp = regInfo{inputs: []regMask{fp64, fp64}, outputs: []regMask{gp}}
121 fp64load = regInfo{inputs: []regMask{gpspsb, 0}, outputs: []regMask{fp64}}
122 fp64store = regInfo{inputs: []regMask{gpspsb, fp64, 0}}
236 …{name: "F32DemoteF64", asm: "F32DemoteF64", argLength: 1, reg: regInfo{inputs: []regMask{fp64}, ou…
274 fpregmask: fp32 | fp64,
[all …]
/dports/lang/go-devel/go-dragonfly-amd64-bootstrap/src/cmd/compile/internal/ssa/gen/
H A DWasmOps.go94 fp64 = buildReg("F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31")
99 callerSave = gp | fp32 | fp64 | buildReg("g")
112 fp64_01 = regInfo{inputs: nil, outputs: []regMask{fp64}}
113 fp64_11 = regInfo{inputs: []regMask{fp64}, outputs: []regMask{fp64}}
114 fp64_21 = regInfo{inputs: []regMask{fp64, fp64}, outputs: []regMask{fp64}}
115 fp64_21gp = regInfo{inputs: []regMask{fp64, fp64}, outputs: []regMask{gp}}
120 fp64load = regInfo{inputs: []regMask{gpspsb, 0}, outputs: []regMask{fp64}}
121 fp64store = regInfo{inputs: []regMask{gpspsb, fp64, 0}}
234 …{name: "F32DemoteF64", asm: "F32DemoteF64", argLength: 1, reg: regInfo{inputs: []regMask{fp64}, ou…
272 fpregmask: fp32 | fp64,
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/tools/clang/test/CodeGenOpenCL/
H A Damdgpu-features.cl17 // GFX904: "target-features"="+16-bit-insts,+ci-insts,+dpp,+fp32-denormals,+fp64-fp16-denormals,+gf…
18 …t-insts,+ci-insts,+dl-insts,+dot1-insts,+dot2-insts,+dpp,+fp32-denormals,+fp64-fp16-denormals,+gfx…
19 …sts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dpp,+fp32-denormals,+fp64-fp16-denormals,+gfx…
20 // GFX1010: "target-features"="+16-bit-insts,+ci-insts,+dl-insts,+dpp,+fp32-denormals,+fp64-fp16-de…
21 …sts,+dot1-insts,+dot2-insts,+dot5-insts,+dot6-insts,+dpp,+fp32-denormals,+fp64-fp16-denormals,+gfx…
22 …sts,+dot1-insts,+dot2-insts,+dot5-insts,+dot6-insts,+dpp,+fp32-denormals,+fp64-fp16-denormals,+gfx…
23 // GFX801: "target-features"="+16-bit-insts,+ci-insts,+dpp,+fp32-denormals,+fp64-fp16-denormals,+gf…
24 // GFX700: "target-features"="+ci-insts,+fp64-fp16-denormals,-fp32-denormals"
25 // GFX600: "target-features"="+fp64-fp16-denormals,-fp32-denormals"
26 // GFX601: "target-features"="+fp64-fp16-denormals,-fp32-denormals"
H A Ddenorms-are-zero.cl20 // RUN: %clang_cc1 -emit-llvm -target-feature +fp32-denormals -target-feature -fp64-fp16-denormals …
21 // RUN: %clang_cc1 -emit-llvm -target-feature +fp32-denormals -target-feature -fp64-fp16-denormals …
35 // explicitly set. amdgcn target always do not flush fp64 denormals. The control for fp64 and fp16 …
39 …{{{[^}]*}} "denorms-are-zero"="false" {{.*}} "target-features"="{{[^"]*}}+fp64-fp16-denormals,{{[^…
40 … {{{[^}]*}} "denorms-are-zero"="true" {{.*}} "target-features"="{{[^"]*}}+fp64-fp16-denormals,{{[^…
42 …ero"="false" {{.*}} "target-features"="{{[^"]*}}+fp32-denormals,{{[^"]*}}+fp64-fp16-denormals{{[^"…
44 …zero"="true" {{.*}} "target-features"="{{[^"]*}}+fp32-denormals,{{[^"]*}}-fp64-fp16-denormals{{[^"…
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/test/CodeGen/MIR/AMDGPU/
H A Dmachine-function-info.ll32 ; CHECK-NEXT: fp64-fp16-input-denormals: true
33 ; CHECK-NEXT: fp64-fp16-output-denormals: true
62 ; CHECK-NEXT: fp64-fp16-input-denormals: true
63 ; CHECK-NEXT: fp64-fp16-output-denormals: true
89 ; CHECK-NEXT: fp64-fp16-input-denormals: true
90 ; CHECK-NEXT: fp64-fp16-output-denormals: true
116 ; CHECK-NEXT: fp64-fp16-input-denormals: true
117 ; CHECK-NEXT: fp64-fp16-output-denormals: true
130 ; CHECK-NEXT: fp64-fp16-input-denormals: true
142 ; CHECK-NEXT: fp64-fp16-input-denormals: true
[all …]
H A Dmachine-function-info-no-ir.mir29 # FULL-NEXT: fp64-fp16-input-denormals: true
30 # FULL-NEXT: fp64-fp16-output-denormals: true
96 # FULL-NEXT: fp64-fp16-input-denormals: true
97 # FULL-NEXT: fp64-fp16-output-denormals: true
134 # FULL-NEXT: fp64-fp16-input-denormals: true
135 # FULL-NEXT: fp64-fp16-output-denormals: true
173 # FULL-NEXT: fp64-fp16-input-denormals: true
174 # FULL-NEXT: fp64-fp16-output-denormals: true
244 # ALL-NEXT: fp64-fp16-input-denormals: false
254 fp64-fp16-input-denormals: false
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/test/CodeGen/MIR/AMDGPU/
H A Dmachine-function-info.ll32 ; CHECK-NEXT: fp64-fp16-input-denormals: true
33 ; CHECK-NEXT: fp64-fp16-output-denormals: true
62 ; CHECK-NEXT: fp64-fp16-input-denormals: true
63 ; CHECK-NEXT: fp64-fp16-output-denormals: true
89 ; CHECK-NEXT: fp64-fp16-input-denormals: true
90 ; CHECK-NEXT: fp64-fp16-output-denormals: true
116 ; CHECK-NEXT: fp64-fp16-input-denormals: true
117 ; CHECK-NEXT: fp64-fp16-output-denormals: true
130 ; CHECK-NEXT: fp64-fp16-input-denormals: true
142 ; CHECK-NEXT: fp64-fp16-input-denormals: true
[all …]
H A Dmachine-function-info-no-ir.mir29 # FULL-NEXT: fp64-fp16-input-denormals: true
30 # FULL-NEXT: fp64-fp16-output-denormals: true
96 # FULL-NEXT: fp64-fp16-input-denormals: true
97 # FULL-NEXT: fp64-fp16-output-denormals: true
134 # FULL-NEXT: fp64-fp16-input-denormals: true
135 # FULL-NEXT: fp64-fp16-output-denormals: true
173 # FULL-NEXT: fp64-fp16-input-denormals: true
174 # FULL-NEXT: fp64-fp16-output-denormals: true
244 # ALL-NEXT: fp64-fp16-input-denormals: false
254 fp64-fp16-input-denormals: false
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/clang/test/CodeGenOpenCL/
H A Damdgpu-features.cl17 …tures"="+16-bit-insts,+ci-insts,+dpp,+flat-address-space,+fp32-denormals,+fp64-fp16-denormals,+gfx…
18 …l-insts,+dot1-insts,+dot2-insts,+dpp,+flat-address-space,+fp32-denormals,+fp64-fp16-denormals,+gfx…
19 …4-insts,+dot5-insts,+dot6-insts,+dpp,+flat-address-space,+fp32-denormals,+fp64-fp16-denormals,+gfx…
20 …6-bit-insts,+ci-insts,+dl-insts,+dpp,+flat-address-space,+fp32-denormals,+fp64-fp16-denormals,+gfx…
21 …2-insts,+dot5-insts,+dot6-insts,+dpp,+flat-address-space,+fp32-denormals,+fp64-fp16-denormals,+gfx…
22 …2-insts,+dot5-insts,+dot6-insts,+dpp,+flat-address-space,+fp32-denormals,+fp64-fp16-denormals,+gfx…
23 …tures"="+16-bit-insts,+ci-insts,+dpp,+flat-address-space,+fp32-denormals,+fp64-fp16-denormals,+gfx…
24 // GFX700: "target-features"="+ci-insts,+flat-address-space,+fp64-fp16-denormals,-fp32-denormals"
25 // GFX600: "target-features"="+fp64-fp16-denormals,-fp32-denormals"
26 // GFX601: "target-features"="+fp64-fp16-denormals,-fp32-denormals"
H A Ddenorms-are-zero.cl20 // RUN: %clang_cc1 -emit-llvm -target-feature +fp32-denormals -target-feature -fp64-fp16-denormals …
21 // RUN: %clang_cc1 -emit-llvm -target-feature +fp32-denormals -target-feature -fp64-fp16-denormals …
35 // explicitly set. amdgcn target always do not flush fp64 denormals. The control for fp64 and fp16 …
39 …{{{[^}]*}} "denorms-are-zero"="false" {{.*}} "target-features"="{{[^"]*}}+fp64-fp16-denormals,{{[^…
40 … {{{[^}]*}} "denorms-are-zero"="true" {{.*}} "target-features"="{{[^"]*}}+fp64-fp16-denormals,{{[^…
42 …ero"="false" {{.*}} "target-features"="{{[^"]*}}+fp32-denormals,{{[^"]*}}+fp64-fp16-denormals{{[^"…
44 …zero"="true" {{.*}} "target-features"="{{[^"]*}}+fp32-denormals,{{[^"]*}}-fp64-fp16-denormals{{[^"…
/dports/devel/llvm10/llvm-10.0.1.src/tools/clang/test/CodeGenOpenCL/
H A Damdgpu-features.cl17 …tures"="+16-bit-insts,+ci-insts,+dpp,+flat-address-space,+fp32-denormals,+fp64-fp16-denormals,+gfx…
18 …l-insts,+dot1-insts,+dot2-insts,+dpp,+flat-address-space,+fp32-denormals,+fp64-fp16-denormals,+gfx…
19 …4-insts,+dot5-insts,+dot6-insts,+dpp,+flat-address-space,+fp32-denormals,+fp64-fp16-denormals,+gfx…
20 …6-bit-insts,+ci-insts,+dl-insts,+dpp,+flat-address-space,+fp32-denormals,+fp64-fp16-denormals,+gfx…
21 …2-insts,+dot5-insts,+dot6-insts,+dpp,+flat-address-space,+fp32-denormals,+fp64-fp16-denormals,+gfx…
22 …2-insts,+dot5-insts,+dot6-insts,+dpp,+flat-address-space,+fp32-denormals,+fp64-fp16-denormals,+gfx…
23 …tures"="+16-bit-insts,+ci-insts,+dpp,+flat-address-space,+fp32-denormals,+fp64-fp16-denormals,+gfx…
24 // GFX700: "target-features"="+ci-insts,+flat-address-space,+fp64-fp16-denormals,-fp32-denormals"
25 // GFX600: "target-features"="+fp64-fp16-denormals,-fp32-denormals"
26 // GFX601: "target-features"="+fp64-fp16-denormals,-fp32-denormals"
H A Ddenorms-are-zero.cl20 // RUN: %clang_cc1 -emit-llvm -target-feature +fp32-denormals -target-feature -fp64-fp16-denormals …
21 // RUN: %clang_cc1 -emit-llvm -target-feature +fp32-denormals -target-feature -fp64-fp16-denormals …
35 // explicitly set. amdgcn target always do not flush fp64 denormals. The control for fp64 and fp16 …
39 …{{{[^}]*}} "denorms-are-zero"="false" {{.*}} "target-features"="{{[^"]*}}+fp64-fp16-denormals,{{[^…
40 … {{{[^}]*}} "denorms-are-zero"="true" {{.*}} "target-features"="{{[^"]*}}+fp64-fp16-denormals,{{[^…
42 …ero"="false" {{.*}} "target-features"="{{[^"]*}}+fp32-denormals,{{[^"]*}}+fp64-fp16-denormals{{[^"…
44 …zero"="true" {{.*}} "target-features"="{{[^"]*}}+fp32-denormals,{{[^"]*}}-fp64-fp16-denormals{{[^"…
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/MIR/AMDGPU/
H A Dmachine-function-info.ll35 ; CHECK-NEXT: fp64-fp16-input-denormals: true
36 ; CHECK-NEXT: fp64-fp16-output-denormals: true
69 ; CHECK-NEXT: fp64-fp16-input-denormals: true
70 ; CHECK-NEXT: fp64-fp16-output-denormals: true
100 ; CHECK-NEXT: fp64-fp16-input-denormals: true
101 ; CHECK-NEXT: fp64-fp16-output-denormals: true
131 ; CHECK-NEXT: fp64-fp16-input-denormals: true
132 ; CHECK-NEXT: fp64-fp16-output-denormals: true
146 ; CHECK-NEXT: fp64-fp16-input-denormals: true
158 ; CHECK-NEXT: fp64-fp16-input-denormals: true
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/MIR/AMDGPU/
H A Dmachine-function-info.ll35 ; CHECK-NEXT: fp64-fp16-input-denormals: true
36 ; CHECK-NEXT: fp64-fp16-output-denormals: true
69 ; CHECK-NEXT: fp64-fp16-input-denormals: true
70 ; CHECK-NEXT: fp64-fp16-output-denormals: true
100 ; CHECK-NEXT: fp64-fp16-input-denormals: true
101 ; CHECK-NEXT: fp64-fp16-output-denormals: true
131 ; CHECK-NEXT: fp64-fp16-input-denormals: true
132 ; CHECK-NEXT: fp64-fp16-output-denormals: true
146 ; CHECK-NEXT: fp64-fp16-input-denormals: true
158 ; CHECK-NEXT: fp64-fp16-input-denormals: true
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/MIR/AMDGPU/
H A Dmachine-function-info.ll35 ; CHECK-NEXT: fp64-fp16-input-denormals: true
36 ; CHECK-NEXT: fp64-fp16-output-denormals: true
69 ; CHECK-NEXT: fp64-fp16-input-denormals: true
70 ; CHECK-NEXT: fp64-fp16-output-denormals: true
100 ; CHECK-NEXT: fp64-fp16-input-denormals: true
101 ; CHECK-NEXT: fp64-fp16-output-denormals: true
131 ; CHECK-NEXT: fp64-fp16-input-denormals: true
132 ; CHECK-NEXT: fp64-fp16-output-denormals: true
146 ; CHECK-NEXT: fp64-fp16-input-denormals: true
158 ; CHECK-NEXT: fp64-fp16-input-denormals: true
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/MIR/AMDGPU/
H A Dmachine-function-info.ll35 ; CHECK-NEXT: fp64-fp16-input-denormals: true
36 ; CHECK-NEXT: fp64-fp16-output-denormals: true
69 ; CHECK-NEXT: fp64-fp16-input-denormals: true
70 ; CHECK-NEXT: fp64-fp16-output-denormals: true
100 ; CHECK-NEXT: fp64-fp16-input-denormals: true
101 ; CHECK-NEXT: fp64-fp16-output-denormals: true
131 ; CHECK-NEXT: fp64-fp16-input-denormals: true
132 ; CHECK-NEXT: fp64-fp16-output-denormals: true
146 ; CHECK-NEXT: fp64-fp16-input-denormals: true
158 ; CHECK-NEXT: fp64-fp16-input-denormals: true
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/MIR/AMDGPU/
H A Dmachine-function-info.ll35 ; CHECK-NEXT: fp64-fp16-input-denormals: true
36 ; CHECK-NEXT: fp64-fp16-output-denormals: true
69 ; CHECK-NEXT: fp64-fp16-input-denormals: true
70 ; CHECK-NEXT: fp64-fp16-output-denormals: true
100 ; CHECK-NEXT: fp64-fp16-input-denormals: true
101 ; CHECK-NEXT: fp64-fp16-output-denormals: true
131 ; CHECK-NEXT: fp64-fp16-input-denormals: true
132 ; CHECK-NEXT: fp64-fp16-output-denormals: true
146 ; CHECK-NEXT: fp64-fp16-input-denormals: true
158 ; CHECK-NEXT: fp64-fp16-input-denormals: true
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/MIR/AMDGPU/
H A Dmachine-function-info.ll35 ; CHECK-NEXT: fp64-fp16-input-denormals: true
36 ; CHECK-NEXT: fp64-fp16-output-denormals: true
69 ; CHECK-NEXT: fp64-fp16-input-denormals: true
70 ; CHECK-NEXT: fp64-fp16-output-denormals: true
100 ; CHECK-NEXT: fp64-fp16-input-denormals: true
101 ; CHECK-NEXT: fp64-fp16-output-denormals: true
131 ; CHECK-NEXT: fp64-fp16-input-denormals: true
132 ; CHECK-NEXT: fp64-fp16-output-denormals: true
146 ; CHECK-NEXT: fp64-fp16-input-denormals: true
158 ; CHECK-NEXT: fp64-fp16-input-denormals: true
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/MIR/AMDGPU/
H A Dmachine-function-info.ll35 ; CHECK-NEXT: fp64-fp16-input-denormals: true
36 ; CHECK-NEXT: fp64-fp16-output-denormals: true
68 ; CHECK-NEXT: fp64-fp16-input-denormals: true
69 ; CHECK-NEXT: fp64-fp16-output-denormals: true
98 ; CHECK-NEXT: fp64-fp16-input-denormals: true
99 ; CHECK-NEXT: fp64-fp16-output-denormals: true
128 ; CHECK-NEXT: fp64-fp16-input-denormals: true
129 ; CHECK-NEXT: fp64-fp16-output-denormals: true
142 ; CHECK-NEXT: fp64-fp16-input-denormals: true
154 ; CHECK-NEXT: fp64-fp16-input-denormals: true
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/MIR/AMDGPU/
H A Dmachine-function-info.ll35 ; CHECK-NEXT: fp64-fp16-input-denormals: true
36 ; CHECK-NEXT: fp64-fp16-output-denormals: true
69 ; CHECK-NEXT: fp64-fp16-input-denormals: true
70 ; CHECK-NEXT: fp64-fp16-output-denormals: true
100 ; CHECK-NEXT: fp64-fp16-input-denormals: true
101 ; CHECK-NEXT: fp64-fp16-output-denormals: true
131 ; CHECK-NEXT: fp64-fp16-input-denormals: true
132 ; CHECK-NEXT: fp64-fp16-output-denormals: true
146 ; CHECK-NEXT: fp64-fp16-input-denormals: true
158 ; CHECK-NEXT: fp64-fp16-input-denormals: true
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/tools/clang/test/CodeGenOpenCL/
H A Damdgpu-features.cl13 // GFX904: "target-features"="+16-bit-insts,+ci-insts,+dpp,+fp32-denormals,+fp64-fp16-denormals,+gf…
14 …ures"="+16-bit-insts,+ci-insts,+dl-insts,+dot-insts,+dpp,+fp32-denormals,+fp64-fp16-denormals,+gfx…
15 // GFX801: "target-features"="+16-bit-insts,+ci-insts,+dpp,+fp32-denormals,+fp64-fp16-denormals,+s-…
16 // GFX700: "target-features"="+ci-insts,+fp64-fp16-denormals,-fp32-denormals"
17 // GFX600: "target-features"="+fp64-fp16-denormals,-fp32-denormals"
18 // GFX601: "target-features"="+fp64-fp16-denormals,-fp32-denormals"
/dports/games/xonotic/Xonotic/source/darkplaces/
H A Dcrypto-keygen-standalone.c251 if(strncasecmp(fp64, prefix, prefixlen)) in fastreject()
255 fp64[fp64size] = 0; in fastreject()
256 if(!strcasestr(fp64, infix)) in fastreject()
263 if(memcmp(fp64, prefix, prefixlen)) in fastreject()
267 fp64[fp64size] = 0; in fastreject()
268 if(!strstr(fp64, infix)) in fastreject()
286 char fp64[513]; size_t fp64size = 512; in main() local
621 printf("%.*s\n", (int)fp64size, fp64); in main()
627 printf("%.*s\n", (int)fp64size, fp64); in main()
653 printf("%.*s\n", (int)fp64size, fp64); in main()
[all …]
/dports/games/darkplaces/darkplaces/
H A Dcrypto-keygen-standalone.c251 if(strncasecmp(fp64, prefix, prefixlen)) in fastreject()
255 fp64[fp64size] = 0; in fastreject()
256 if(!strcasestr(fp64, infix)) in fastreject()
263 if(memcmp(fp64, prefix, prefixlen)) in fastreject()
267 fp64[fp64size] = 0; in fastreject()
268 if(!strstr(fp64, infix)) in fastreject()
286 char fp64[513]; size_t fp64size = 512; in main() local
621 printf("%.*s\n", (int)fp64size, fp64); in main()
627 printf("%.*s\n", (int)fp64size, fp64); in main()
653 printf("%.*s\n", (int)fp64size, fp64); in main()
[all …]
/dports/devel/llvm70/llvm-7.0.1.src/tools/clang/test/CodeGenOpenCL/
H A Ddenorms-are-zero.cl5 // RUN: %clang_cc1 -emit-llvm -target-feature +fp32-denormals -target-feature -fp64-fp16-denormals …
17 // explicitly set. amdgcn target always do not flush fp64 denormals. The control for fp64 and fp16 …
20 … {{{[^}]*}} "denorms-are-zero"="true" {{.*}} "target-features"="{{[^"]*}}+fp64-fp16-denormals,{{[^…
22 …{{{[^}]*}} "denorms-are-zero"="false" {{.*}} "target-features"="{{[^"]*}}+fp64-fp16-denormals,{{[^…
24 …zero"="true" {{.*}} "target-features"="{{[^"]*}}+fp32-denormals,{{[^"]*}}-fp64-fp16-denormals{{[^"…

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