| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 55 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
60 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
65 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
255 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
277 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
279 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
508 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
626 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
627 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
717 if (getRegBank(SrcReg, MRI, TRI) == &AArch64::FPRRegBank) in getInstrMapping()
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 55 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
60 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
65 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
255 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
277 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
279 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
508 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
626 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
627 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
717 if (getRegBank(SrcReg, MRI, TRI) == &AArch64::FPRRegBank) in getInstrMapping()
[all …]
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 55 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
60 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
65 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
255 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
277 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
279 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
508 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
626 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
627 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
717 if (getRegBank(SrcReg, MRI, TRI) == &AArch64::FPRRegBank) in getInstrMapping()
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 54 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
59 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
64 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
254 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
275 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
277 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
508 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
628 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
629 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
719 if (getRegBank(SrcReg, MRI, TRI) == &AArch64::FPRRegBank) in getInstrMapping()
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 55 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
60 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
65 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
255 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
277 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
279 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
508 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
626 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
627 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
717 if (getRegBank(SrcReg, MRI, TRI) == &AArch64::FPRRegBank) in getInstrMapping()
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 55 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
60 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
65 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
255 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
277 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
279 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
508 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
626 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
627 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
717 if (getRegBank(SrcReg, MRI, TRI) == &AArch64::FPRRegBank) in getInstrMapping()
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64RegisterBankInfo.cpp | 52 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
57 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
62 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
241 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
255 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
257 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
499 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
500 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
610 getRegBank(UseMI.getOperand(0).getReg(), MRI, TRI) == in getInstrMapping()
631 getRegBank(DefMI->getOperand(0).getReg(), MRI, TRI) == in getInstrMapping()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64RegisterBankInfo.cpp | 52 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
57 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
62 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
241 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
255 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
257 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
498 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
499 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
609 getRegBank(UseMI.getOperand(0).getReg(), MRI, TRI) == in getInstrMapping()
630 getRegBank(DefMI->getOperand(0).getReg(), MRI, TRI) == in getInstrMapping()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 51 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
56 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
61 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
248 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
268 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
270 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
485 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
601 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
602 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
689 if (getRegBank(SrcReg, MRI, TRI) == &AArch64::FPRRegBank) in getInstrMapping()
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 51 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
56 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
61 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
248 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
268 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
270 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
485 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
601 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
602 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
689 if (getRegBank(SrcReg, MRI, TRI) == &AArch64::FPRRegBank) in getInstrMapping()
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 51 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
56 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
61 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
248 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
268 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
270 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
485 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
601 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
602 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
669 if (getRegBank(ScalarReg, MRI, TRI) == &AArch64::FPRRegBank || in getInstrMapping()
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 50 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
55 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
60 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
247 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
266 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
268 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
482 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) == in hasFPConstraints()
581 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
582 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
649 if (getRegBank(ScalarReg, MRI, TRI) == &AArch64::FPRRegBank || in getInstrMapping()
[all …]
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 50 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
55 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
60 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
247 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
267 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
269 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
483 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) == in hasFPConstraints()
582 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
583 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
650 if (getRegBank(ScalarReg, MRI, TRI) == &AArch64::FPRRegBank || in getInstrMapping()
[all …]
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64RegisterBankInfo.cpp | 51 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
56 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
61 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
241 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
260 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
262 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
476 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) == in hasFPConstraints()
574 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
575 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
751 if (getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank || in getInstrMapping()
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterBankInfo.cpp | 51 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
56 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
61 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
241 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
260 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
262 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
476 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) == in hasFPConstraints()
574 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
575 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
751 if (getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank || in getInstrMapping()
[all …]
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterBankInfo.cpp | 51 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
56 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
61 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
241 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
260 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
262 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
476 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) == in hasFPConstraints()
574 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
575 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
751 if (getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank || in getInstrMapping()
[all …]
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64RegisterBankInfo.cpp | 51 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
56 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
61 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
240 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
259 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
261 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
475 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) == in hasFPConstraints()
573 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
574 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
745 if (getRegBank(VReg, MRI, TRI) == &AArch64::FPRRegBank || in getInstrMapping()
[all …]
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 124 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
178 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
183 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
188 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
209 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
408 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
750 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
751 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
823 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
824 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
[all …]
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 160 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
214 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
219 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
224 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
466 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
808 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
809 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
881 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
882 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
248 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
253 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
518 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
919 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
920 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
1014 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
1015 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
[all …]
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
250 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
255 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
277 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
520 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
921 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
922 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
1016 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
1017 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
248 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
253 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
518 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
919 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
920 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
1014 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
1015 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
248 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
253 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
518 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
919 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
920 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
1014 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
1015 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
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| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
248 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
253 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
518 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
919 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
920 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
1014 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
1015 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
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| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
245 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
250 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
255 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
277 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
520 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
921 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
922 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
1016 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
1017 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
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