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Searched refs:get_all_wires (Results 1 – 2 of 2) sorted by relevance

/dports/cad/yosys/yosys-yosys-0.12/kernel/
H A Drtlil.cc3150 RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this)); in Wire()
3157 RTLIL::Wire::get_all_wires()->erase(hashidx_); in ~Wire()
3163 std::map<unsigned int, RTLIL::Wire*> *RTLIL::Wire::get_all_wires(void) in get_all_wires() function in RTLIL::Wire
H A Drtlil.h1475 static std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);