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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/
H A Dmb_timing.xdc33 [get_pins cat_io_lvds_dual_mode_i0/BUFGCTRL_radio_clk/O]
39 [get_pins cat_io_lvds_dual_mode_i0/BUFGCTRL_radio_clk/O]
50 [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_0]]]
55 [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_1]]]
60 [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_2]]]
65 [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_3]]]
70 [get_pins {e320_clocking_i/mmcm_adv_inst/CLKOUT0}]
100 set_max_delay -from [get_pins sfp_wrapper_i/mgt_io_i/mdio_master_i/mdc_reg/C] \
116 set_false_path -from [get_pins bus_reset_gen/reset_out_reg/C] \
118 set_false_path -from [get_pins bus_reset_gen/reset_out_reg/C] \
[all …]
H A De320_1ge.xdc10 set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks -of_objects [get_pins …
11 set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks -of_objects [get_pins …
13 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*reset_sy…
14 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*/pma_res…
15 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/mgt_io_i/one_gige_phy_i/*/pma_res…
H A De320_dram.xdc12 [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKOUT1}]
14 [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKFBOUT}]
19 [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT}]
23 [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0}]
27 [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT5}]
H A De320_aurora.xdc7 create_generated_clock -name aurora_init_clk [get_pins -hierarchical -filter {NAME =~ "*aurora_clk_…
11 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "sfp_wrapper_*/mgt_io_i/aurora_phy*/aur…
13 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "*npio*/aurora_phy*/aurora_64b66b_pcs_p…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e31x/
H A De31x_timing.xdc27 -name bus_clk [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/FCLKCLK[0]}]
31 -name clk40 [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/FCLKCLK[1]}]
35 # -name bus_clk [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/FCLKCLK[3]}]
50 create_generated_clock -name CAT_FB_CLK -multiply_by 1 -source [get_pins e310_io/oddr_clk/C] [get_p…
94 set_max_delay -from [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0MO] \
98 set_max_delay -from [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0SCLKO] \
102 set_max_delay -from [get_pins {e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0SSON[0]}] \
107 … -to [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0MI] 10.000 -datapath_only
109 -to [get_pins e31x_ps_bd_inst/processing_system7_0/inst/PS7_i/EMIOSPI0MI] 1.000
140 set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].val…
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/
H A Dx300_1ge.xdc14 set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks -of_objects [get_pins…
15 set_clock_groups -asynchronous -group [get_clocks bus_clk] -group [get_clocks -of_objects [get_pins…
17 set_false_path -to [get_pins -hier -filter {NAME =~ *sfpp_io_*/one_gige_phy_i/*reset_sync*/PRE}]
18 set_false_path -to [get_pins -hier -filter {NAME =~ *sfpp_io_*/one_gige_phy_i/*/pma_reset_pipe_reg*…
19 set_false_path -to [get_pins -hier -filter {NAME =~ *sfpp_io_*/one_gige_phy_i/*/pma_reset_pipe*[0]/…
H A Dx300_aurora.xdc12 create_generated_clock -name aurora_init_clk [get_pins -hierarchical -filter {NAME =~ "*aurora_clk_…
16 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "*sfpp_io_*/*/rst_sync_sys_rst_i/*auror…
H A Dx300_dram.xdc5 create_generated_clock -name ddr3_axi_clk [get_pins -hierarchical -filter {NAME =~ "*u_ddr3_infr…
6 create_generated_clock -name ddr3_axi_clk_x2 [get_pins -hierarchical -filter {NAME =~ "*u_ddr3_infr…
H A Dtiming.xdc48 create_generated_clock -name DB0_DAC_DCI -source [get_pins gen_db0/oddr_clk/C] -divide_by 1 [get_p…
49 create_generated_clock -name DB1_DAC_DCI -source [get_pins gen_db1/oddr_clk/C] -divide_by 1 [get_p…
61 create_generated_clock -name bus_clk [get_pins -hierarchical -filter {NAME =~ "*bu…
62 create_generated_clock -name bus_clk_div2 [get_pins -hierarchical -filter {NAME =~ "*bu…
63 create_generated_clock -name ce_clk [get_pins -hierarchical -filter {NAME =~ "*bu…
64 create_generated_clock -name ioport2_clk [get_pins -hierarchical -filter {NAME =~ "*bu…
591 set_max_delay -to [get_pins {int_reset_sync/reset_int*/PRE}] 12.000
592 set_max_delay -to [get_pins {int_div2_reset_sync/reset_int*/PRE}] 12.000
593 set_max_delay -to [get_pins {ce_reset_sync/reset_int*/PRE}] 12.000
594 set_max_delay -to [get_pins {radio_reset_sync/reset_int*/PRE}] 10.000
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/
H A Dn310_1ge.xdc10 set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks -of_objects [get_pins …
11 set_clock_groups -asynchronous -group [get_clocks clk100] -group [get_clocks -of_objects [get_pins …
13 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige…
14 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige…
15 set_false_path -to [get_pins -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].lane_i/mgt_io_i/one_gige…
H A Dmb_clocks.xdc45 [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_0]]]
48 [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_1]]]
51 [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_2]]]
54 [get_pins [get_property SOURCE_PINS [get_clocks clk_fpga_3]]]
64 create_generated_clock -name meas_clk_fb [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_…
65 create_generated_clock -name meas_clk [get_pins {n3xx_clocking_i/misc_clock_gen_i/inst/mmcm_adv_…
73 -source [get_pins [all_fanin -flat -only_cells -startpoints_only $WR_OUT_CLK]/C] \
84 -source [get_pins [all_fanin -flat -only_cells -startpoints_only $FP_GPIO_CLK]/C] \
H A Dn310_aurora.xdc7 create_generated_clock -name aurora_init_clk [get_pins -hierarchical -filter {NAME =~ "*aurora_clk_…
11 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "sfp_wrapper_*/lanes[*].lane_i/mgt_io_i…
13 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "*npio*/aurora_phy*/aurora_64b66b_pcs_p…
15 set_false_path -to [get_pins -hierarchical -filter {NAME =~ "qsfp_wrapper_i/lanes[*].lane_i/mgt_io_…
H A Dn310_dram.xdc13 [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKOUT1}]
15 [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i/CLKFBOUT}]
20 [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT}]
24 [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT0}]
28 [get_pins {u_ddr3_32bit/u_ddr3_32bit_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKOUT5}]
H A Dn3xx_wr.xdc12 [get_pins -hierarchical -filter \
17 [get_pins -hierarchical -filter \
22 …[get_pins -hierarchical -filter {NAME=~sfp_wrapper_0/*/cmp_xwrc_platform/gen_default_plls.gen_kint…
26 …[get_pins -hierarchical -filter {NAME=~sfp_wrapper_0/*/cmp_xwrc_platform/gen_default_plls.gen_kint…
67 # -to [get_pins -hierarchical -filter {NAME =~ */sync_posedge.sync0_reg/D}]
78 # -to [get_pins -hierarchical -filter {NAME =~ */U_Wrapped_Softpll/tags_masked_reg…
H A Dn310_10ge.xdc18 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].l…
19 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ sfp_wrapper_*/lanes[*].l…
21 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ qsfp_wrapper_i/lanes[*].…
22 set_false_path -to [get_pins -of_objects [get_cells -hier -filter {NAME =~ qsfp_wrapper_i/lanes[*].…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/rh/
H A Ddb_clocks.xdc66 create_generated_clock -name radio_clk_fb [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKFBOU…
67 create_generated_clock -name radio_clk [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT0…
68 create_generated_clock -name radio_clk_2x [get_pins {dba_core/RadioClockingx/RadioClkMmcm/CLKOUT1…
71 create_generated_clock -name radio_clk_b [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT0…
72 create_generated_clock -name radio_clk_b_2x [get_pins {dbb_core/RadioClockingx/RadioClkMmcm/CLKOUT1…
93 -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_A]/C] \
97 -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_A]/C] \
101 -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_B]/C] \
105 -source [get_pins [all_fanin -flat -only_cells -startpoints_only $PL_SPI_CLK_B]/C] \
112 -source [get_pins {inst_n310_ps/jtag_0/U0/bitq_ctrl/bitq_state_reg[1]/C}] \
[all …]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/chipscope_icon.constraints/
H A Dchipscope_icon.xdc2 create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB…
3 …LK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICO…
4 set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAM…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/
H A Dchipscope_icon.xdc2 create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB…
3 …LK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICO…
4 set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAM…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/b200_chipscope_icon.constraints/
H A Db200_chipscope_icon.xdc2 create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB…
3 …LK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICO…
4 set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAM…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/
H A Dchipscope_icon.xdc2 create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB…
3 …LK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICO…
4 set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAM…
H A Db200_chipscope_icon.xdc2 create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB…
3 …LK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICO…
4 set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAM…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/chipscope_icon.constraints/
H A Dchipscope_icon.xdc2 create_clock -name J_CLK -period 30 -waveform {15 30} [get_pins -of [get_cells -hier * -filter {LIB…
3 …LK -source [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {name =~ */U_ICO…
4 set_false_path -through [get_pins -of [get_cells -hier * -filter {LIB_CELL =~ BSCAN*}] -filter {NAM…
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/
H A Done_gige_phy.xdc153 set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_rd_addrgray*/da…
154 set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_wr_addrgray*/da…
157 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe…
158 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe…
159 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe…
161 set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }]
163 set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe_reg*/PRE}]
164 set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe*[0]/D}]
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/
H A Done_gige_phy.xdc153 set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_rd_addrgray*/da…
154 set_false_path -to [get_pins -hier -filter {name =~ *tx_elastic_buffer_inst/reclock_wr_addrgray*/da…
157 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe…
158 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe…
159 set_false_path -from [get_clocks gmii_tx_clk] -to [get_pins -hier -filter {name =~ tx_elastic_buffe…
161 set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }]
163 set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe_reg*/PRE}]
164 set_false_path -to [get_pins -hier -filter {name =~ */core_resets_i/pma_reset_pipe*[0]/D}]
/dports/cad/openroad/OpenROAD-2.0/src/rsz/test/
H A Dfanin_fanout1.tcl6 report_object_full_names [rsz::find_fanin_fanouts [get_pins r3/D]]
7 report_object_full_names [rsz::find_fanin_fanouts [get_pins r1/D]]

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