1/* 2 ******************************************************************************* 3 * 4 * FIFO Generator - Verilog Behavioral Model 5 * 6 ******************************************************************************* 7 * 8 * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. 9 * 10 * This file contains confidential and proprietary information 11 * of Xilinx, Inc. and is protected under U.S. and 12 * international copyright and other intellectual property 13 * laws. 14 * 15 * DISCLAIMER 16 * This disclaimer is not a license and does not grant any 17 * rights to the materials distributed herewith. Except as 18 * otherwise provided in a valid license issued to you by 19 * Xilinx, and to the maximum extent permitted by applicable 20 * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 21 * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 22 * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 23 * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 24 * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 25 * (2) Xilinx shall not be liable (whether in contract or tort, 26 * including negligence, or under any other theory of 27 * liability) for any loss or damage of any kind or nature 28 * related to, arising under or in connection with these 29 * materials, including for any direct, or any indirect, 30 * special, incidental, or consequential loss or damage 31 * (including loss of data, profits, goodwill, or any type of 32 * loss or damage suffered as a result of any action brought 33 * by a third party) even if such damage or loss was 34 * reasonably foreseeable or Xilinx had been advised of the 35 * possibility of the same. 36 * 37 * CRITICAL APPLICATIONS 38 * Xilinx products are not designed or intended to be fail- 39 * safe, or for use in any application requiring fail-safe 40 * performance, such as life-support or safety devices or 41 * systems, Class III medical devices, nuclear facilities, 42 * applications related to the deployment of airbags, or any 43 * other applications that could lead to death, personal 44 * injury, or severe property or environmental damage 45 * (individually and collectively, "Critical 46 * Applications"). Customer assumes the sole risk and 47 * liability of any use of Xilinx products in Critical 48 * Applications, subject only to applicable laws and 49 * regulations governing limitations on product liability. 50 * 51 * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 52 * PART OF THIS FILE AT ALL TIMES. 53 * 54 ******************************************************************************* 55 ******************************************************************************* 56 * 57 * Filename: FIFO_GENERATOR_V6_1.v 58 * 59 * Author : Xilinx 60 * 61 ******************************************************************************* 62 * Structure: 63 * 64 * fifo_generator_v6_1.vhd 65 * | 66 * +-fifo_generator_v6_1_bhv_ver_as 67 * | 68 * +-fifo_generator_v6_1_bhv_ver_ss 69 * | 70 * +-fifo_generator_v6_1_bhv_ver_preload0 71 * 72 ******************************************************************************* 73 * Description: 74 * 75 * The Verilog behavioral model for the FIFO Generator. 76 * 77 * The behavioral model has three parts: 78 * - The behavioral model for independent clocks FIFOs (_as) 79 * - The behavioral model for common clock FIFOs (_ss) 80 * - The "preload logic" block which implements First-word Fall-through 81 * 82 ******************************************************************************* 83 * Description: 84 * The verilog behavioral model for the FIFO generator core. 85 * 86 ******************************************************************************* 87 */ 88 89`timescale 1ps/1ps 90`ifndef TCQ 91 `define TCQ 100 92`endif 93 94 95/******************************************************************************* 96 * Declaration of top-level module 97 ******************************************************************************/ 98module FIFO_GENERATOR_V6_1 99 #( 100 parameter C_COMMON_CLOCK = 0, 101 parameter C_COUNT_TYPE = 0, 102 parameter C_DATA_COUNT_WIDTH = 2, 103 parameter C_DEFAULT_VALUE = "", 104 parameter C_DIN_WIDTH = 8, 105 parameter C_DOUT_RST_VAL = "", 106 parameter C_DOUT_WIDTH = 8, 107 parameter C_ENABLE_RLOCS = 0, 108 parameter C_FAMILY = "virtex6", //Not allowed in Verilog model 109 parameter C_FULL_FLAGS_RST_VAL = 1, 110 parameter C_HAS_ALMOST_EMPTY = 0, 111 parameter C_HAS_ALMOST_FULL = 0, 112 parameter C_HAS_BACKUP = 0, 113 parameter C_HAS_DATA_COUNT = 0, 114 parameter C_HAS_INT_CLK = 0, 115 parameter C_HAS_MEMINIT_FILE = 0, 116 parameter C_HAS_OVERFLOW = 0, 117 parameter C_HAS_RD_DATA_COUNT = 0, 118 parameter C_HAS_RD_RST = 0, 119 parameter C_HAS_RST = 0, 120 parameter C_HAS_SRST = 0, 121 parameter C_HAS_UNDERFLOW = 0, 122 parameter C_HAS_VALID = 0, 123 parameter C_HAS_WR_ACK = 0, 124 parameter C_HAS_WR_DATA_COUNT = 0, 125 parameter C_HAS_WR_RST = 0, 126 parameter C_IMPLEMENTATION_TYPE = 0, 127 parameter C_INIT_WR_PNTR_VAL = 0, 128 parameter C_MEMORY_TYPE = 1, 129 parameter C_MIF_FILE_NAME = "", 130 parameter C_OPTIMIZATION_MODE = 0, 131 parameter C_OVERFLOW_LOW = 0, 132 parameter C_PRELOAD_LATENCY = 1, 133 parameter C_PRELOAD_REGS = 0, 134 parameter C_PRIM_FIFO_TYPE = "", 135 parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, 136 parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, 137 parameter C_PROG_EMPTY_TYPE = 0, 138 parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, 139 parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, 140 parameter C_PROG_FULL_TYPE = 0, 141 parameter C_RD_DATA_COUNT_WIDTH = 2, 142 parameter C_RD_DEPTH = 256, 143 parameter C_RD_FREQ = 1, 144 parameter C_RD_PNTR_WIDTH = 8, 145 parameter C_UNDERFLOW_LOW = 0, 146 parameter C_USE_DOUT_RST = 0, 147 parameter C_USE_ECC = 0, 148 parameter C_USE_EMBEDDED_REG = 0, 149 parameter C_USE_FIFO16_FLAGS = 0, 150 parameter C_USE_FWFT_DATA_COUNT = 0, 151 parameter C_VALID_LOW = 0, 152 parameter C_WR_ACK_LOW = 0, 153 parameter C_WR_DATA_COUNT_WIDTH = 2, 154 parameter C_WR_DEPTH = 256, 155 parameter C_WR_FREQ = 1, 156 parameter C_WR_PNTR_WIDTH = 8, 157 parameter C_WR_RESPONSE_LATENCY = 1, 158 parameter C_MSGON_VAL = 1, 159 parameter C_ENABLE_RST_SYNC = 1, 160 parameter C_ERROR_INJECTION_TYPE = 0 161 ) 162 163 ( 164 input BACKUP, 165 input BACKUP_MARKER, 166 input CLK, 167 input RST, 168 input SRST, 169 input WR_CLK, 170 input WR_RST, 171 input RD_CLK, 172 input RD_RST, 173 input [C_DIN_WIDTH-1:0] DIN, 174 input WR_EN, 175 input RD_EN, 176 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, 177 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, 178 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, 179 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, 180 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, 181 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, 182 input INT_CLK, 183 input INJECTDBITERR, 184 input INJECTSBITERR, 185 186 output [C_DOUT_WIDTH-1:0] DOUT, 187 output FULL, 188 output ALMOST_FULL, 189 output WR_ACK, 190 output OVERFLOW, 191 output EMPTY, 192 output ALMOST_EMPTY, 193 output VALID, 194 output UNDERFLOW, 195 output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, 196 output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, 197 output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, 198 output PROG_FULL, 199 output PROG_EMPTY, 200 output SBITERR, 201 output DBITERR 202 ); 203 204/* 205 ****************************************************************************** 206 * Definition of Parameters 207 ****************************************************************************** 208 * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) 209 * C_COUNT_TYPE : *not used 210 * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus 211 * C_DEFAULT_VALUE : *not used 212 * C_DIN_WIDTH : Width of DIN bus 213 * C_DOUT_RST_VAL : Reset value of DOUT 214 * C_DOUT_WIDTH : Width of DOUT bus 215 * C_ENABLE_RLOCS : *not used 216 * C_FAMILY : not used in bhv model 217 * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) 218 * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag 219 * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag 220 * C_HAS_BACKUP : *not used 221 * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus 222 * C_HAS_INT_CLK : not used in bhv model 223 * C_HAS_MEMINIT_FILE : *not used 224 * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag 225 * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus 226 * C_HAS_RD_RST : *not used 227 * C_HAS_RST : 1=Core has Async Rst 228 * C_HAS_SRST : 1=Core has Sync Rst 229 * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag 230 * C_HAS_VALID : 1=Core has VALID flag 231 * C_HAS_WR_ACK : 1=Core has WR_ACK flag 232 * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus 233 * C_HAS_WR_RST : *not used 234 * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram 235 * 1=Common-Clock ShiftRam 236 * 2=Indep. Clocks Bram/Dram 237 * 3=Virtex-4 Built-in 238 * 4=Virtex-5 Built-in 239 * C_INIT_WR_PNTR_VAL : *not used 240 * C_MEMORY_TYPE : 1=Block RAM 241 * 2=Distributed RAM 242 * 3=Shift RAM 243 * 4=Built-in FIFO 244 * C_MIF_FILE_NAME : *not used 245 * C_OPTIMIZATION_MODE : *not used 246 * C_OVERFLOW_LOW : 1=OVERFLOW active low 247 * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 248 * C_PRELOAD_REGS : 1=Use output registers 249 * C_PRIM_FIFO_TYPE : not used in bhv model 250 * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold 251 * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold 252 * C_PROG_EMPTY_TYPE : 0=No programmable empty 253 * 1=Single prog empty thresh constant 254 * 2=Multiple prog empty thresh constants 255 * 3=Single prog empty thresh input 256 * 4=Multiple prog empty thresh inputs 257 * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold 258 * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold 259 * C_PROG_FULL_TYPE : 0=No prog full 260 * 1=Single prog full thresh constant 261 * 2=Multiple prog full thresh constants 262 * 3=Single prog full thresh input 263 * 4=Multiple prog full thresh inputs 264 * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus 265 * C_RD_DEPTH : Depth of read interface (2^N) 266 * C_RD_FREQ : not used in bhv model 267 * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) 268 * C_UNDERFLOW_LOW : 1=UNDERFLOW active low 269 * C_USE_DOUT_RST : 1=Resets DOUT on RST 270 * C_USE_ECC : Used for error injection purpose 271 * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register 272 * C_USE_FIFO16_FLAGS : not used in bhv model 273 * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count 274 * C_VALID_LOW : 1=VALID active low 275 * C_WR_ACK_LOW : 1=WR_ACK active low 276 * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus 277 * C_WR_DEPTH : Depth of write interface (2^N) 278 * C_WR_FREQ : not used in bhv model 279 * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) 280 * C_WR_RESPONSE_LATENCY : *not used 281 * C_MSGON_VAL : *not used by bhv model 282 * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST 283 * 1 = Use RST 284 * C_ERROR_INJECTION_TYPE : 0 = No error injection 285 * 1 = Single bit error injection only 286 * 2 = Double bit error injection only 287 * 3 = Single and double bit error injection 288 ****************************************************************************** 289 * Definition of Ports 290 ****************************************************************************** 291 * BACKUP : Not used 292 * BACKUP_MARKER: Not used 293 * CLK : Clock 294 * DIN : Input data bus 295 * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag 296 * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag 297 * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag 298 * PROG_FULL_THRESH : Threshold for Programmable Full Flag 299 * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag 300 * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag 301 * RD_CLK : Read Domain Clock 302 * RD_EN : Read enable 303 * RD_RST : Read Reset 304 * RST : Asynchronous Reset 305 * SRST : Synchronous Reset 306 * WR_CLK : Write Domain Clock 307 * WR_EN : Write enable 308 * WR_RST : Write Reset 309 * INT_CLK : Internal Clock 310 * INJECTSBITERR: Inject Signle bit error 311 * INJECTDBITERR: Inject Double bit error 312 * ALMOST_EMPTY : One word remaining in FIFO 313 * ALMOST_FULL : One empty space remaining in FIFO 314 * DATA_COUNT : Number of data words in fifo( synchronous to CLK) 315 * DOUT : Output data bus 316 * EMPTY : Empty flag 317 * FULL : Full flag 318 * OVERFLOW : Last write rejected 319 * PROG_EMPTY : Programmable Empty Flag 320 * PROG_FULL : Programmable Full Flag 321 * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) 322 * UNDERFLOW : Last read rejected 323 * VALID : Last read acknowledged, DOUT bus VALID 324 * WR_ACK : Last write acknowledged 325 * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) 326 * SBITERR : Single Bit ECC Error Detected 327 * DBITERR : Double Bit ECC Error Detected 328 ****************************************************************************** 329 */ 330 331 332 /***************************************************************************** 333 * Derived parameters 334 ****************************************************************************/ 335 //There are 2 Verilog behavioral models 336 // 0 = Common-Clock FIFO/ShiftRam FIFO 337 // 1 = Independent Clocks FIFO 338 parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0; 339 340 //Internal reset signals 341 reg rd_rst_asreg = 0; 342 reg rd_rst_asreg_d1 = 0; 343 reg rd_rst_asreg_d2 = 0; 344 reg rd_rst_reg = 0; 345 wire rd_rst_comb; 346 reg rd_rst_d1 = 0; 347 reg wr_rst_asreg = 0; 348 reg wr_rst_asreg_d1 = 0; 349 reg wr_rst_asreg_d2 = 0; 350 reg wr_rst_reg = 0; 351 wire wr_rst_comb; 352 wire wr_rst_i; 353 wire rd_rst_i; 354 wire rst_i; 355 356 //Internal reset signals 357 reg rst_asreg = 0; 358 reg rst_asreg_d1 = 0; 359 reg rst_asreg_d2 = 0; 360 reg rst_reg = 0; 361 wire rst_comb; 362 wire rst_full_gen_i; 363 wire rst_full_ff_i; 364 365 wire RD_CLK_P0_IN; 366 wire RST_P0_IN; 367 wire RD_EN_FIFO_IN; 368 wire RD_EN_P0_IN; 369 370 wire ALMOST_EMPTY_FIFO_OUT; 371 wire ALMOST_FULL_FIFO_OUT; 372 wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; 373 wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; 374 wire EMPTY_FIFO_OUT; 375 wire FULL_FIFO_OUT; 376 wire OVERFLOW_FIFO_OUT; 377 wire PROG_EMPTY_FIFO_OUT; 378 wire PROG_FULL_FIFO_OUT; 379 wire VALID_FIFO_OUT; 380 wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; 381 wire UNDERFLOW_FIFO_OUT; 382 wire WR_ACK_FIFO_OUT; 383 wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; 384 385 386 //*************************************************************************** 387 // Internal Signals 388 // The core uses either the internal_ wires or the preload0_ wires depending 389 // on whether the core uses Preload0 or not. 390 // When using preload0, the internal signals connect the internal core to 391 // the preload logic, and the external core's interfaces are tied to the 392 // preload0 signals from the preload logic. 393 //*************************************************************************** 394 wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; 395 wire VALID_P0_OUT; 396 wire EMPTY_P0_OUT; 397 wire ALMOSTEMPTY_P0_OUT; 398 reg EMPTY_P0_OUT_Q; 399 reg ALMOSTEMPTY_P0_OUT_Q; 400 wire UNDERFLOW_P0_OUT; 401 wire RDEN_P0_OUT; 402 wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; 403 wire EMPTY_P0_IN; 404 reg [31:0] DATA_COUNT_FWFT; 405 reg SS_FWFT_WR ; 406 reg SS_FWFT_RD ; 407 408 wire sbiterr_fifo_out; 409 wire dbiterr_fifo_out; 410 411 // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR. 412 assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ? 413 INJECTSBITERR : 0; 414 assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ? 415 INJECTDBITERR : 0; 416 417 418// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL 419// parameter (1=Independent Clocks, 0=Common Clock) 420 421 localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL; 422generate 423case (C_VERILOG_IMPL) 4240 : begin : block1 425 //Common Clock Behavioral Model 426 fifo_generator_v6_1_bhv_ver_ss 427 #( 428 C_DATA_COUNT_WIDTH, 429 C_DIN_WIDTH, 430 C_DOUT_RST_VAL, 431 C_DOUT_WIDTH, 432// C_FULL_FLAGS_RST_VAL, 433 FULL_FLAGS_RST_VAL, 434 C_HAS_ALMOST_EMPTY, 435 C_HAS_ALMOST_FULL, 436 C_HAS_DATA_COUNT, 437 C_HAS_OVERFLOW, 438 C_HAS_RD_DATA_COUNT, 439 C_HAS_RST, 440 C_HAS_SRST, 441 C_HAS_UNDERFLOW, 442 C_HAS_VALID, 443 C_HAS_WR_ACK, 444 C_HAS_WR_DATA_COUNT, 445 C_IMPLEMENTATION_TYPE, 446 C_MEMORY_TYPE, 447 C_OVERFLOW_LOW, 448 C_PRELOAD_LATENCY, 449 C_PRELOAD_REGS, 450 C_PROG_EMPTY_THRESH_ASSERT_VAL, 451 C_PROG_EMPTY_THRESH_NEGATE_VAL, 452 C_PROG_EMPTY_TYPE, 453 C_PROG_FULL_THRESH_ASSERT_VAL, 454 C_PROG_FULL_THRESH_NEGATE_VAL, 455 C_PROG_FULL_TYPE, 456 C_RD_DATA_COUNT_WIDTH, 457 C_RD_DEPTH, 458 C_RD_PNTR_WIDTH, 459 C_UNDERFLOW_LOW, 460 C_USE_DOUT_RST, 461 C_USE_EMBEDDED_REG, 462 C_USE_FWFT_DATA_COUNT, 463 C_VALID_LOW, 464 C_WR_ACK_LOW, 465 C_WR_DATA_COUNT_WIDTH, 466 C_WR_DEPTH, 467 C_WR_PNTR_WIDTH, 468 C_USE_ECC, 469 C_ENABLE_RST_SYNC, 470 C_ERROR_INJECTION_TYPE 471 ) 472 gen_ss 473 ( 474 .CLK (CLK), 475 .RST (rst_i), 476 .SRST (SRST), 477 .RST_FULL_GEN (rst_full_gen_i), 478 .RST_FULL_FF (rst_full_ff_i), 479 .DIN (DIN), 480 .WR_EN (WR_EN), 481 .RD_EN (RD_EN_FIFO_IN), 482 .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), 483 .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), 484 .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), 485 .PROG_FULL_THRESH (PROG_FULL_THRESH), 486 .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), 487 .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), 488 .INJECTSBITERR (inject_sbit_err), 489 .INJECTDBITERR (inject_dbit_err), 490 .DOUT (DOUT_FIFO_OUT), 491 .FULL (FULL_FIFO_OUT), 492 .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), 493 .WR_ACK (WR_ACK_FIFO_OUT), 494 .OVERFLOW (OVERFLOW_FIFO_OUT), 495 .EMPTY (EMPTY_FIFO_OUT), 496 .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), 497 .VALID (VALID_FIFO_OUT), 498 .UNDERFLOW (UNDERFLOW_FIFO_OUT), 499 .DATA_COUNT (DATA_COUNT_FIFO_OUT), 500 .PROG_FULL (PROG_FULL_FIFO_OUT), 501 .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), 502 .SBITERR (sbiterr_fifo_out), 503 .DBITERR (dbiterr_fifo_out) 504 ); 505end 5061 : begin : block1 507 //Independent Clocks Behavioral Model 508 fifo_generator_v6_1_bhv_ver_as 509 #( 510 C_DATA_COUNT_WIDTH, 511 C_DIN_WIDTH, 512 C_DOUT_RST_VAL, 513 C_DOUT_WIDTH, 514 C_FULL_FLAGS_RST_VAL, 515 C_HAS_ALMOST_EMPTY, 516 C_HAS_ALMOST_FULL, 517 C_HAS_DATA_COUNT, 518 C_HAS_OVERFLOW, 519 C_HAS_RD_DATA_COUNT, 520 C_HAS_RST, 521 C_HAS_UNDERFLOW, 522 C_HAS_VALID, 523 C_HAS_WR_ACK, 524 C_HAS_WR_DATA_COUNT, 525 C_IMPLEMENTATION_TYPE, 526 C_MEMORY_TYPE, 527 C_OVERFLOW_LOW, 528 C_PRELOAD_LATENCY, 529 C_PRELOAD_REGS, 530 C_PROG_EMPTY_THRESH_ASSERT_VAL, 531 C_PROG_EMPTY_THRESH_NEGATE_VAL, 532 C_PROG_EMPTY_TYPE, 533 C_PROG_FULL_THRESH_ASSERT_VAL, 534 C_PROG_FULL_THRESH_NEGATE_VAL, 535 C_PROG_FULL_TYPE, 536 C_RD_DATA_COUNT_WIDTH, 537 C_RD_DEPTH, 538 C_RD_PNTR_WIDTH, 539 C_UNDERFLOW_LOW, 540 C_USE_DOUT_RST, 541 C_USE_EMBEDDED_REG, 542 C_USE_FWFT_DATA_COUNT, 543 C_VALID_LOW, 544 C_WR_ACK_LOW, 545 C_WR_DATA_COUNT_WIDTH, 546 C_WR_DEPTH, 547 C_WR_PNTR_WIDTH, 548 C_USE_ECC, 549 C_ENABLE_RST_SYNC, 550 C_ERROR_INJECTION_TYPE 551 ) 552 gen_as 553 ( 554 .WR_CLK (WR_CLK), 555 .RD_CLK (RD_CLK), 556 .RST (rst_i), 557 .RST_FULL_GEN (rst_full_gen_i), 558 .RST_FULL_FF (rst_full_ff_i), 559 .WR_RST (wr_rst_i), 560 .RD_RST (rd_rst_i), 561 .DIN (DIN), 562 .WR_EN (WR_EN), 563 .RD_EN (RD_EN_FIFO_IN), 564 .RD_EN_USER (RD_EN), 565 .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), 566 .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), 567 .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), 568 .PROG_FULL_THRESH (PROG_FULL_THRESH), 569 .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), 570 .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), 571 .INJECTSBITERR (inject_sbit_err), 572 .INJECTDBITERR (inject_dbit_err), 573 .USER_EMPTY_FB (EMPTY_P0_OUT), 574 .DOUT (DOUT_FIFO_OUT), 575 .FULL (FULL_FIFO_OUT), 576 .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), 577 .WR_ACK (WR_ACK_FIFO_OUT), 578 .OVERFLOW (OVERFLOW_FIFO_OUT), 579 .EMPTY (EMPTY_FIFO_OUT), 580 .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), 581 .VALID (VALID_FIFO_OUT), 582 .UNDERFLOW (UNDERFLOW_FIFO_OUT), 583 .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), 584 .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), 585 .PROG_FULL (PROG_FULL_FIFO_OUT), 586 .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), 587 .SBITERR (sbiterr_fifo_out), 588 .DBITERR (dbiterr_fifo_out) 589 ); 590end 591 592default : begin : block1 593 //Independent Clocks Behavioral Model 594 fifo_generator_v6_1_bhv_ver_as 595 #( 596 C_DATA_COUNT_WIDTH, 597 C_DIN_WIDTH, 598 C_DOUT_RST_VAL, 599 C_DOUT_WIDTH, 600 C_FULL_FLAGS_RST_VAL, 601 C_HAS_ALMOST_EMPTY, 602 C_HAS_ALMOST_FULL, 603 C_HAS_DATA_COUNT, 604 C_HAS_OVERFLOW, 605 C_HAS_RD_DATA_COUNT, 606 C_HAS_RST, 607 C_HAS_UNDERFLOW, 608 C_HAS_VALID, 609 C_HAS_WR_ACK, 610 C_HAS_WR_DATA_COUNT, 611 C_IMPLEMENTATION_TYPE, 612 C_MEMORY_TYPE, 613 C_OVERFLOW_LOW, 614 C_PRELOAD_LATENCY, 615 C_PRELOAD_REGS, 616 C_PROG_EMPTY_THRESH_ASSERT_VAL, 617 C_PROG_EMPTY_THRESH_NEGATE_VAL, 618 C_PROG_EMPTY_TYPE, 619 C_PROG_FULL_THRESH_ASSERT_VAL, 620 C_PROG_FULL_THRESH_NEGATE_VAL, 621 C_PROG_FULL_TYPE, 622 C_RD_DATA_COUNT_WIDTH, 623 C_RD_DEPTH, 624 C_RD_PNTR_WIDTH, 625 C_UNDERFLOW_LOW, 626 C_USE_DOUT_RST, 627 C_USE_EMBEDDED_REG, 628 C_USE_FWFT_DATA_COUNT, 629 C_VALID_LOW, 630 C_WR_ACK_LOW, 631 C_WR_DATA_COUNT_WIDTH, 632 C_WR_DEPTH, 633 C_WR_PNTR_WIDTH, 634 C_USE_ECC, 635 C_ENABLE_RST_SYNC, 636 C_ERROR_INJECTION_TYPE 637 ) 638 gen_as 639 ( 640 .WR_CLK (WR_CLK), 641 .RD_CLK (RD_CLK), 642 .RST (rst_i), 643 .RST_FULL_GEN (rst_full_gen_i), 644 .RST_FULL_FF (rst_full_ff_i), 645 .WR_RST (wr_rst_i), 646 .RD_RST (rd_rst_i), 647 .DIN (DIN), 648 .WR_EN (WR_EN), 649 .RD_EN (RD_EN_FIFO_IN), 650 .RD_EN_USER (RD_EN), 651 .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), 652 .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), 653 .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), 654 .PROG_FULL_THRESH (PROG_FULL_THRESH), 655 .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), 656 .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), 657 .INJECTSBITERR (inject_sbit_err), 658 .INJECTDBITERR (inject_dbit_err), 659 .USER_EMPTY_FB (EMPTY_P0_OUT), 660 .DOUT (DOUT_FIFO_OUT), 661 .FULL (FULL_FIFO_OUT), 662 .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), 663 .WR_ACK (WR_ACK_FIFO_OUT), 664 .OVERFLOW (OVERFLOW_FIFO_OUT), 665 .EMPTY (EMPTY_FIFO_OUT), 666 .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), 667 .VALID (VALID_FIFO_OUT), 668 .UNDERFLOW (UNDERFLOW_FIFO_OUT), 669 .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), 670 .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), 671 .PROG_FULL (PROG_FULL_FIFO_OUT), 672 .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), 673 .SBITERR (sbiterr_fifo_out), 674 .DBITERR (dbiterr_fifo_out) 675 ); 676end 677 678endcase 679endgenerate 680 681 682 //************************************************************************** 683 // Connect Internal Signals 684 // (Signals labeled internal_*) 685 // In the normal case, these signals tie directly to the FIFO's inputs and 686 // outputs. 687 // In the case of Preload Latency 0 or 1, there are intermediate 688 // signals between the internal FIFO and the preload logic. 689 //************************************************************************** 690 691 692 //*********************************************** 693 // If First-Word Fall-Through, instantiate 694 // the preload0 (FWFT) module 695 //*********************************************** 696 generate 697 if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin : block2 698 699 700 fifo_generator_v6_1_bhv_ver_preload0 701 #( 702 C_DOUT_RST_VAL, 703 C_DOUT_WIDTH, 704 C_HAS_RST, 705 C_ENABLE_RST_SYNC, 706 C_HAS_SRST, 707 C_USE_DOUT_RST, 708 C_USE_ECC, 709 C_VALID_LOW, 710 C_UNDERFLOW_LOW, 711 C_MEMORY_TYPE 712 ) 713 fgpl0 714 ( 715 .RD_CLK (RD_CLK_P0_IN), 716 .RD_RST (RST_P0_IN), 717 .SRST (SRST), 718 .RD_EN (RD_EN_P0_IN), 719 .FIFOEMPTY (EMPTY_P0_IN), 720 .FIFODATA (DATA_P0_IN), 721 .FIFOSBITERR (sbiterr_fifo_out), 722 .FIFODBITERR (dbiterr_fifo_out), 723 .USERDATA (DATA_P0_OUT), 724 .USERVALID (VALID_P0_OUT), 725 .USEREMPTY (EMPTY_P0_OUT), 726 .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), 727 .USERUNDERFLOW (UNDERFLOW_P0_OUT), 728 .RAMVALID (RAMVALID_P0_OUT), 729 .FIFORDEN (RDEN_P0_OUT), 730 .USERSBITERR (SBITERR), 731 .USERDBITERR (DBITERR) 732 ); 733 734 735 //*********************************************** 736 // Connect inputs to preload (FWFT) module 737 //*********************************************** 738 //Connect the RD_CLK of the Preload (FWFT) module to CLK if we 739 // have a common-clock FIFO, or RD_CLK if we have an 740 // independent clock FIFO 741 assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); 742 assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0; 743 assign RD_EN_P0_IN = RD_EN; 744 assign EMPTY_P0_IN = EMPTY_FIFO_OUT; 745 assign DATA_P0_IN = DOUT_FIFO_OUT; 746 747 //*********************************************** 748 // Connect outputs from preload (FWFT) module 749 //*********************************************** 750 assign DOUT = DATA_P0_OUT; 751 assign VALID = VALID_P0_OUT ; 752 assign EMPTY = EMPTY_P0_OUT; 753 assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; 754 assign UNDERFLOW = UNDERFLOW_P0_OUT ; 755 756 assign RD_EN_FIFO_IN = RDEN_P0_OUT; 757 758 759 //*********************************************** 760 // Create DATA_COUNT from First-Word Fall-Through 761 // data count 762 //*********************************************** 763 assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: 764 (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : 765 DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; 766 767 //*********************************************** 768 // Create DATA_COUNT from First-Word Fall-Through 769 // data count 770 //*********************************************** 771 always @ (posedge RD_CLK or posedge RST_P0_IN) begin 772 if (RST_P0_IN) begin 773 EMPTY_P0_OUT_Q <= #`TCQ 1; 774 ALMOSTEMPTY_P0_OUT_Q <= #`TCQ 1; 775 end else begin 776 EMPTY_P0_OUT_Q <= #`TCQ EMPTY_P0_OUT; 777 ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT; 778 end 779 end //always 780 781 782 //*********************************************** 783 // logic for common-clock data count when FWFT is selected 784 //*********************************************** 785 initial begin 786 SS_FWFT_RD = 1'b0; 787 DATA_COUNT_FWFT = 0 ; 788 SS_FWFT_WR = 1'b0 ; 789 end //initial 790 791 792 //*********************************************** 793 // common-clock data count is implemented as an 794 // up-down counter. SS_FWFT_WR and SS_FWFT_RD 795 // are the up/down enables for the counter. 796 //*********************************************** 797 always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT) begin 798 if (C_VALID_LOW == 1) begin 799 SS_FWFT_RD = RD_EN && ~VALID_P0_OUT ; 800 end else begin 801 SS_FWFT_RD = RD_EN && VALID_P0_OUT ; 802 end 803 SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; 804 end 805 806 //*********************************************** 807 // common-clock data count is implemented as an 808 // up-down counter for FWFT. This always block 809 // calculates the counter. 810 //*********************************************** 811 always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin 812 if (RST_P0_IN) begin 813 DATA_COUNT_FWFT <= #`TCQ 0; 814 end else begin 815 if (SRST && (C_HAS_SRST == 1) ) begin 816 DATA_COUNT_FWFT <= #`TCQ 0; 817 end else begin 818 case ( {SS_FWFT_WR, SS_FWFT_RD}) 819 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; 820 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ; 821 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ; 822 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; 823 endcase 824 end //if SRST 825 end //IF RST 826 end //always 827 828 829 end else begin : block2 //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) 830 831 //*********************************************** 832 // If NOT First-Word Fall-Through, wire the outputs 833 // of the internal _ss or _as FIFO directly to the 834 // output, and do not instantiate the preload0 835 // module. 836 //*********************************************** 837 838 assign RD_CLK_P0_IN = 0; 839 assign RST_P0_IN = 0; 840 assign RD_EN_P0_IN = 0; 841 842 assign RD_EN_FIFO_IN = RD_EN; 843 844 assign DOUT = DOUT_FIFO_OUT; 845 assign DATA_P0_IN = 0; 846 assign VALID = VALID_FIFO_OUT; 847 assign EMPTY = EMPTY_FIFO_OUT; 848 assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; 849 assign EMPTY_P0_IN = 0; 850 assign UNDERFLOW = UNDERFLOW_FIFO_OUT; 851 assign DATA_COUNT = DATA_COUNT_FIFO_OUT; 852 assign SBITERR = sbiterr_fifo_out; 853 assign DBITERR = dbiterr_fifo_out; 854 855 end //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) 856 endgenerate 857 858 859 //*********************************************** 860 // Connect user flags to internal signals 861 //*********************************************** 862 863 //If we are using extra logic for the FWFT data count, then override the 864 //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. 865 //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. 866 generate 867 if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ) begin : block3 868 assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); 869 end //block3 870 endgenerate 871 872 //If we are using extra logic for the FWFT data count, then override the 873 //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. 874 //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. 875 generate 876 if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) ) begin : block30 877 assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); 878 end //block30 879 endgenerate 880 881 //If we are not using extra logic for the FWFT data count, 882 //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the 883 //internal FIFO instance 884 generate 885 if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 886 assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; 887 end 888 endgenerate 889 890 //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal 891 //FIFO instance 892 generate 893 if (C_USE_FWFT_DATA_COUNT==1) begin : block4 894 assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; 895 end 896 else begin : block4 897 assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; 898 end 899 endgenerate 900 901 902 //Connect other flags to the internal FIFO instance 903 assign FULL = FULL_FIFO_OUT; 904 assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; 905 assign WR_ACK = WR_ACK_FIFO_OUT; 906 assign OVERFLOW = OVERFLOW_FIFO_OUT; 907 assign PROG_FULL = PROG_FULL_FIFO_OUT; 908 assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; 909 910 911 // if an asynchronous FIFO has been selected, display a message that the FIFO 912 // will not be cycle-accurate in simulation 913 initial begin 914 if (C_IMPLEMENTATION_TYPE == 2) begin 915 $display("WARNING: Behavioral models for independent clock FIFO configurations are not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); 916 end else if (C_MEMORY_TYPE == 4) begin 917 $display("FAILURE : Behavioral models for Virtex-4, Virtex-5 and Virtex-6 built-in FIFO configurations is currently not supported. Please select the structural simulation model option in CORE Generator. You can enable this in CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); 918 $finish; 919 end 920 end //initial 921 922 /************************************************************************** 923 * Internal reset logic 924 **************************************************************************/ 925 assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0; 926 assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0; 927 assign rst_i = C_HAS_RST ? rst_reg : 0; 928 929 wire rst_2_sync; 930 wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK; 931 generate 932 if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync 933 always @* begin 934 wr_rst_reg <= WR_RST; 935 rd_rst_reg <= RD_RST; 936 rst_reg <= 1'b0; 937 end 938 assign rst_2_sync = WR_RST; 939 end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : gic_rst 940 assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; 941 assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; 942 assign rst_2_sync = RST; 943 944 always @(posedge WR_CLK or posedge RST) begin 945 if (RST == 1'b1) begin 946 wr_rst_asreg <= #`TCQ 1'b1; 947 end else begin 948 if (wr_rst_asreg_d1 == 1'b1) begin 949 wr_rst_asreg <= #`TCQ 1'b0; 950 end else begin 951 wr_rst_asreg <= #`TCQ wr_rst_asreg; 952 end 953 end 954 end 955 956 always @(posedge WR_CLK) begin 957 wr_rst_asreg_d1 <= #`TCQ wr_rst_asreg; 958 wr_rst_asreg_d2 <= #`TCQ wr_rst_asreg_d1; 959 end 960 961 always @(posedge WR_CLK or posedge wr_rst_comb) begin 962 if (wr_rst_comb == 1'b1) begin 963 wr_rst_reg <= #`TCQ 1'b1; 964 end else begin 965 wr_rst_reg <= #`TCQ 1'b0; 966 end 967 end 968 969 always @(posedge RD_CLK or posedge RST) begin 970 if (RST == 1'b1) begin 971 rd_rst_asreg <= #`TCQ 1'b1; 972 end else begin 973 if (rd_rst_asreg_d1 == 1'b1) begin 974 rd_rst_asreg <= #`TCQ 1'b0; 975 end else begin 976 rd_rst_asreg <= #`TCQ rd_rst_asreg; 977 end 978 end 979 end 980 981 always @(posedge RD_CLK) begin 982 rd_rst_asreg_d1 <= #`TCQ rd_rst_asreg; 983 rd_rst_asreg_d2 <= #`TCQ rd_rst_asreg_d1; 984 end 985 986 always @(posedge RD_CLK or posedge rd_rst_comb) begin 987 if (rd_rst_comb == 1'b1) begin 988 rd_rst_reg <= #`TCQ 1'b1; 989 end else begin 990 rd_rst_reg <= #`TCQ 1'b0; 991 end 992 end 993 end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : gcc_rst 994 assign rst_comb = !rst_asreg_d2 && rst_asreg; 995 assign rst_2_sync = RST; 996 997 always @(posedge CLK or posedge RST) begin 998 if (RST == 1'b1) begin 999 rst_asreg <= #`TCQ 1'b1; 1000 end else begin 1001 if (rst_asreg_d1 == 1'b1) begin 1002 rst_asreg <= #`TCQ 1'b0; 1003 end else begin 1004 rst_asreg <= #`TCQ rst_asreg; 1005 end 1006 end 1007 end 1008 1009 always @(posedge CLK) begin 1010 rst_asreg_d1 <= #`TCQ rst_asreg; 1011 rst_asreg_d2 <= #`TCQ rst_asreg_d1; 1012 end 1013 1014 always @(posedge CLK or posedge rst_comb) begin 1015 if (rst_comb == 1'b1) begin 1016 rst_reg <= #`TCQ 1'b1; 1017 end else begin 1018 rst_reg <= #`TCQ 1'b0; 1019 end 1020 end 1021 end 1022 endgenerate 1023 1024 reg rst_d1 = 1'b0; 1025 reg rst_d2 = 1'b0; 1026 reg rst_d3 = 1'b0; 1027 reg rst_d4 = 1'b0; 1028 generate 1029 if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1 1030 // RST_FULL_GEN replaces the reset falling edge detection used to de-assert 1031 // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1. 1032 1033 // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL & 1034 // PROG_FULL 1035 1036 always @ (posedge rst_2_sync or posedge clk_2_sync) begin 1037 if (rst_2_sync) begin 1038 rst_d1 <= 1'b1; 1039 rst_d2 <= 1'b1; 1040 rst_d3 <= 1'b1; 1041 rst_d4 <= 1'b0; 1042 end else begin 1043 if (SRST) begin 1044 rst_d1 <= #`TCQ 1'b1; 1045 rst_d2 <= #`TCQ 1'b1; 1046 rst_d3 <= #`TCQ 1'b1; 1047 rst_d4 <= #`TCQ 1'b0; 1048 end else begin 1049 rst_d1 <= #`TCQ 1'b0; 1050 rst_d2 <= #`TCQ rst_d1; 1051 rst_d3 <= #`TCQ rst_d2; 1052 rst_d4 <= #`TCQ rst_d3; 1053 end 1054 end 1055 end 1056 assign rst_full_ff_i = (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ; 1057 assign rst_full_gen_i = rst_d4; 1058 1059 end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full 1060 assign rst_full_gen_i = 1'b0; 1061 assign rst_full_ff_i = (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i; 1062 end 1063 endgenerate 1064 1065endmodule //FIFO_GENERATOR_V6_1 1066 1067 1068 1069/******************************************************************************* 1070 * Declaration of Independent-Clocks FIFO Module 1071 ******************************************************************************/ 1072module fifo_generator_v6_1_bhv_ver_as 1073 1074 /*************************************************************************** 1075 * Declare user parameters and their defaults 1076 ***************************************************************************/ 1077 #( 1078 parameter C_DATA_COUNT_WIDTH = 2, 1079 parameter C_DIN_WIDTH = 8, 1080 parameter C_DOUT_RST_VAL = "", 1081 parameter C_DOUT_WIDTH = 8, 1082 parameter C_FULL_FLAGS_RST_VAL = 1, 1083 parameter C_HAS_ALMOST_EMPTY = 0, 1084 parameter C_HAS_ALMOST_FULL = 0, 1085 parameter C_HAS_DATA_COUNT = 0, 1086 parameter C_HAS_OVERFLOW = 0, 1087 parameter C_HAS_RD_DATA_COUNT = 0, 1088 parameter C_HAS_RST = 0, 1089 parameter C_HAS_UNDERFLOW = 0, 1090 parameter C_HAS_VALID = 0, 1091 parameter C_HAS_WR_ACK = 0, 1092 parameter C_HAS_WR_DATA_COUNT = 0, 1093 parameter C_IMPLEMENTATION_TYPE = 0, 1094 parameter C_MEMORY_TYPE = 1, 1095 parameter C_OVERFLOW_LOW = 0, 1096 parameter C_PRELOAD_LATENCY = 1, 1097 parameter C_PRELOAD_REGS = 0, 1098 parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, 1099 parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, 1100 parameter C_PROG_EMPTY_TYPE = 0, 1101 parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, 1102 parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, 1103 parameter C_PROG_FULL_TYPE = 0, 1104 parameter C_RD_DATA_COUNT_WIDTH = 2, 1105 parameter C_RD_DEPTH = 256, 1106 parameter C_RD_PNTR_WIDTH = 8, 1107 parameter C_UNDERFLOW_LOW = 0, 1108 parameter C_USE_DOUT_RST = 0, 1109 parameter C_USE_EMBEDDED_REG = 0, 1110 parameter C_USE_FWFT_DATA_COUNT = 0, 1111 parameter C_VALID_LOW = 0, 1112 parameter C_WR_ACK_LOW = 0, 1113 parameter C_WR_DATA_COUNT_WIDTH = 2, 1114 parameter C_WR_DEPTH = 256, 1115 parameter C_WR_PNTR_WIDTH = 8, 1116 parameter C_USE_ECC = 0, 1117 parameter C_ENABLE_RST_SYNC = 1, 1118 parameter C_ERROR_INJECTION_TYPE = 0 1119 ) 1120 1121 /*************************************************************************** 1122 * Declare Input and Output Ports 1123 ***************************************************************************/ 1124 ( 1125 input [C_DIN_WIDTH-1:0] DIN, 1126 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, 1127 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, 1128 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, 1129 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, 1130 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, 1131 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, 1132 input RD_CLK, 1133 input RD_EN, 1134 input RD_EN_USER, 1135 input RST, 1136 input RST_FULL_GEN, 1137 input RST_FULL_FF, 1138 input WR_RST, 1139 input RD_RST, 1140 input WR_CLK, 1141 input WR_EN, 1142 input INJECTDBITERR, 1143 input INJECTSBITERR, 1144 input USER_EMPTY_FB, 1145 output reg ALMOST_EMPTY = 1'b1, 1146 output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL, 1147 output [C_DOUT_WIDTH-1:0] DOUT, 1148 output reg EMPTY = 1'b1, 1149 output reg FULL = C_FULL_FLAGS_RST_VAL, 1150 output OVERFLOW, 1151 output PROG_EMPTY, 1152 output PROG_FULL, 1153 output VALID, 1154 output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, 1155 output UNDERFLOW, 1156 output WR_ACK, 1157 output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, 1158 output SBITERR, 1159 output DBITERR 1160 ); 1161 1162 reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; 1163 reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; 1164 reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; 1165 1166 1167 /*************************************************************************** 1168 * Parameters used as constants 1169 **************************************************************************/ 1170 //When RST is present, set FULL reset value to '1'. 1171 //If core has no RST, make sure FULL powers-on as '0'. 1172 parameter C_DEPTH_RATIO_WR = 1173 (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; 1174 parameter C_DEPTH_RATIO_RD = 1175 (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; 1176 parameter C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; 1177 parameter C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; 1178 1179 // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC 1180 // -----------------|------------------|-----------------|--------------- 1181 // 1 | 8 | C_RD_PNTR_WIDTH | 2 1182 // 1 | 4 | C_RD_PNTR_WIDTH | 2 1183 // 1 | 2 | C_RD_PNTR_WIDTH | 2 1184 // 1 | 1 | C_WR_PNTR_WIDTH | 2 1185 // 2 | 1 | C_WR_PNTR_WIDTH | 4 1186 // 4 | 1 | C_WR_PNTR_WIDTH | 8 1187 // 8 | 1 | C_WR_PNTR_WIDTH | 16 1188 1189 localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; 1190 wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); 1191 1192 parameter [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; 1193 1194 parameter [31:0] log2_reads_per_write = log2_val(reads_per_write); 1195 1196 parameter [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; 1197 1198 parameter [31:0] log2_writes_per_read = log2_val(writes_per_read); 1199 1200 1201 1202 /************************************************************************** 1203 * FIFO Contents Tracking and Data Count Calculations 1204 *************************************************************************/ 1205 1206 // Memory which will be used to simulate a FIFO 1207 reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; 1208 // Local parameters used to determine whether to inject ECC error or not 1209 localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; 1210 localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; 1211 localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; 1212 // Array that holds the error injection type (single/double bit error) on 1213 // a specific write operation, which is returned on read to corrupt the 1214 // output data. 1215 reg [1:0] ecc_err[C_WR_DEPTH-1:0]; 1216 1217 //The amount of data stored in the FIFO at any time is given 1218 // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK 1219 // domain. 1220 //num_wr_bits is calculated by considering the total words in the FIFO, 1221 // and the state of the read pointer (which may not have yet crossed clock 1222 // domains.) 1223 //num_rd_bits is calculated by considering the total words in the FIFO, 1224 // and the state of the write pointer (which may not have yet crossed clock 1225 // domains.) 1226 reg [31:0] num_wr_bits; 1227 reg [31:0] num_rd_bits; 1228 reg [31:0] next_num_wr_bits; 1229 reg [31:0] next_num_rd_bits; 1230 1231 //The write pointer - tracks write operations 1232 // (Works opposite to core: wr_ptr is a DOWN counter) 1233 reg [31:0] wr_ptr; 1234 reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. 1235 reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; 1236 reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; 1237 reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; 1238 wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; 1239 reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; 1240 wire wr_rst_i = WR_RST; 1241 reg wr_rst_d1 =0; 1242 1243 //The read pointer - tracks read operations 1244 // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) 1245 reg [31:0] rd_ptr; 1246 reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. 1247 reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; 1248 reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; 1249 reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; 1250 reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; 1251 wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; 1252 reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; 1253 wire rd_rst_i = RD_RST; 1254 wire ram_rd_en; 1255 reg ram_rd_en_d1 = 1'b0; 1256 1257 1258 // Delayed ram_rd_en is needed only for STD Embedded register option 1259 generate 1260 if (C_PRELOAD_LATENCY == 2) begin : grd_d 1261 always @ (posedge RD_CLK or posedge rd_rst_i) begin 1262 if (rd_rst_i) 1263 ram_rd_en_d1 <= #`TCQ 1'b0; 1264 else 1265 ram_rd_en_d1 <= #`TCQ ram_rd_en; 1266 end 1267 end 1268 endgenerate 1269 1270 // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation 1271 generate 1272 if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth 1273 assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; 1274 assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0; 1275 end else begin : rdl // Read depth lesser than or equal to write depth 1276 assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; 1277 end 1278 endgenerate 1279 1280 // Generate Empty and Almost Empty 1281 // ram_rd_en used to determine EMPTY should depend on the EMPTY. 1282 assign ram_rd_en = RD_EN & !EMPTY; 1283 assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1)))); 1284 assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2)))); 1285 1286 // Register Empty and Almost Empty 1287 always @ (posedge RD_CLK or posedge rd_rst_i) 1288 begin 1289 if (rd_rst_i) begin 1290 EMPTY <= #`TCQ 1'b1; 1291 ALMOST_EMPTY <= #`TCQ 1'b1; 1292 rd_data_count_int <= #`TCQ {C_RD_PNTR_WIDTH-1{1'b0}}; 1293 end else begin 1294 rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0}; 1295 1296 if (empty_int) 1297 EMPTY <= #`TCQ 1'b1; 1298 else 1299 EMPTY <= #`TCQ 1'b0; 1300 1301 if (!EMPTY) begin 1302 if (almost_empty_int) 1303 ALMOST_EMPTY <= #`TCQ 1'b1; 1304 else 1305 ALMOST_EMPTY <= #`TCQ 1'b0; 1306 end 1307 end // rd_rst_i 1308 end // always 1309 1310 // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation 1311 generate 1312 if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth 1313 assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; 1314 assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0; 1315 end else begin : wdl // Write depth lesser than or equal to read depth 1316 assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; 1317 end 1318 endgenerate 1319 1320 // Generate FULL and ALMOST_FULL 1321 // ram_wr_en used to determine FULL should depend on the FULL. 1322 assign ram_wr_en = WR_EN & !FULL; 1323 assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2)))); 1324 assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3)))); 1325 1326 // Register FULL and ALMOST_FULL Empty 1327 always @ (posedge WR_CLK or posedge RST_FULL_FF) 1328 begin 1329 if (RST_FULL_FF) begin 1330 FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; 1331 ALMOST_FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; 1332 wr_data_count_int <= #`TCQ {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; 1333 end else begin 1334 wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0}; 1335 if (full_int) begin 1336 FULL <= #`TCQ 1'b1; 1337 end else begin 1338 FULL <= #`TCQ 1'b0; 1339 end 1340 1341 if (RST_FULL_GEN) begin 1342 ALMOST_FULL <= #`TCQ 1'b0; 1343 end else if (!FULL) begin 1344 if (almost_full_int) 1345 ALMOST_FULL <= #`TCQ 1'b1; 1346 else 1347 ALMOST_FULL <= #`TCQ 1'b0; 1348 end 1349 end // wr_rst_i 1350 end // always 1351 1352 // Determine which stage in FWFT registers are valid 1353 reg stage1_valid = 0; 1354 reg stage2_valid = 0; 1355 generate 1356 if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc 1357 always @ (posedge RD_CLK or posedge rd_rst_i) begin 1358 if (rd_rst_i) begin 1359 stage1_valid <= #`TCQ 0; 1360 stage2_valid <= #`TCQ 0; 1361 end else begin 1362 1363 if (!stage1_valid && !stage2_valid) begin 1364 if (!EMPTY) 1365 stage1_valid <= #`TCQ 1'b1; 1366 else 1367 stage1_valid <= #`TCQ 1'b0; 1368 end else if (stage1_valid && !stage2_valid) begin 1369 if (EMPTY) begin 1370 stage1_valid <= #`TCQ 1'b0; 1371 stage2_valid <= #`TCQ 1'b1; 1372 end else begin 1373 stage1_valid <= #`TCQ 1'b1; 1374 stage2_valid <= #`TCQ 1'b1; 1375 end 1376 end else if (!stage1_valid && stage2_valid) begin 1377 if (EMPTY && RD_EN_USER) begin 1378 stage1_valid <= #`TCQ 1'b0; 1379 stage2_valid <= #`TCQ 1'b0; 1380 end else if (!EMPTY && RD_EN_USER) begin 1381 stage1_valid <= #`TCQ 1'b1; 1382 stage2_valid <= #`TCQ 1'b0; 1383 end else if (!EMPTY && !RD_EN_USER) begin 1384 stage1_valid <= #`TCQ 1'b1; 1385 stage2_valid <= #`TCQ 1'b1; 1386 end else begin 1387 stage1_valid <= #`TCQ 1'b0; 1388 stage2_valid <= #`TCQ 1'b1; 1389 end 1390 end else if (stage1_valid && stage2_valid) begin 1391 if (EMPTY && RD_EN_USER) begin 1392 stage1_valid <= #`TCQ 1'b0; 1393 stage2_valid <= #`TCQ 1'b1; 1394 end else begin 1395 stage1_valid <= #`TCQ 1'b1; 1396 stage2_valid <= #`TCQ 1'b1; 1397 end 1398 end else begin 1399 stage1_valid <= #`TCQ 1'b0; 1400 stage2_valid <= #`TCQ 1'b0; 1401 end 1402 end // rd_rst_i 1403 end // always 1404 end 1405 endgenerate 1406 1407 //Pointers passed into opposite clock domain 1408 reg [31:0] wr_ptr_rdclk; 1409 reg [31:0] wr_ptr_rdclk_next; 1410 reg [31:0] rd_ptr_wrclk; 1411 reg [31:0] rd_ptr_wrclk_next; 1412 1413 //Amount of data stored in the FIFO scaled to the narrowest (deepest) port 1414 // (Do not include data in FWFT stages) 1415 //Used to calculate PROG_EMPTY. 1416 wire [31:0] num_read_words_pe = 1417 num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); 1418 1419 //Amount of data stored in the FIFO scaled to the narrowest (deepest) port 1420 // (Do not include data in FWFT stages) 1421 //Used to calculate PROG_FULL. 1422 wire [31:0] num_write_words_pf = 1423 num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); 1424 1425 /************************** 1426 * Read Data Count 1427 *************************/ 1428 1429 reg [31:0] num_read_words_dc; 1430 reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; 1431 1432 always @(num_rd_bits) begin 1433 if (C_USE_FWFT_DATA_COUNT) begin 1434 1435 //If using extra logic for FWFT Data Counts, 1436 // then scale FIFO contents to read domain, 1437 // and add two read words for FWFT stages 1438 //This value is only a temporary value and not used in the code. 1439 num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); 1440 1441 //Trim the read words for use with RD_DATA_COUNT 1442 num_read_words_sized_i = 1443 num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; 1444 1445 end else begin 1446 1447 //If not using extra logic for FWFT Data Counts, 1448 // then scale FIFO contents to read domain. 1449 //This value is only a temporary value and not used in the code. 1450 num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; 1451 1452 //Trim the read words for use with RD_DATA_COUNT 1453 num_read_words_sized_i = 1454 num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; 1455 1456 end //if (C_USE_FWFT_DATA_COUNT) 1457 end //always 1458 1459 1460 /************************** 1461 * Write Data Count 1462 *************************/ 1463 1464 reg [31:0] num_write_words_dc; 1465 reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; 1466 1467 always @(num_wr_bits) begin 1468 if (C_USE_FWFT_DATA_COUNT) begin 1469 1470 //Calculate the Data Count value for the number of write words, 1471 // when using First-Word Fall-Through with extra logic for Data 1472 // Counts. This takes into consideration the number of words that 1473 // are expected to be stored in the FWFT register stages (it always 1474 // assumes they are filled). 1475 //This value is scaled to the Write Domain. 1476 //The expression (((A-1)/B))+1 divides A/B, but takes the 1477 // ceiling of the result. 1478 //When num_wr_bits==0, set the result manually to prevent 1479 // division errors. 1480 //EXTRA_WORDS_DC is the number of words added to write_words 1481 // due to FWFT. 1482 //This value is only a temporary value and not used in the code. 1483 num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; 1484 1485 //Trim the write words for use with WR_DATA_COUNT 1486 num_write_words_sized_i = 1487 num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; 1488 1489 end else begin 1490 1491 //Calculate the Data Count value for the number of write words, when NOT 1492 // using First-Word Fall-Through with extra logic for Data Counts. This 1493 // calculates only the number of words in the internal FIFO. 1494 //The expression (((A-1)/B))+1 divides A/B, but takes the 1495 // ceiling of the result. 1496 //This value is scaled to the Write Domain. 1497 //When num_wr_bits==0, set the result manually to prevent 1498 // division errors. 1499 //This value is only a temporary value and not used in the code. 1500 num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; 1501 1502 //Trim the read words for use with RD_DATA_COUNT 1503 num_write_words_sized_i = 1504 num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; 1505 1506 end //if (C_USE_FWFT_DATA_COUNT) 1507 end //always 1508 1509 1510 1511 /*************************************************************************** 1512 * Internal registers and wires 1513 **************************************************************************/ 1514 1515 //Temporary signals used for calculating the model's outputs. These 1516 //are only used in the assign statements immediately following wire, 1517 //parameter, and function declarations. 1518 wire [C_DOUT_WIDTH-1:0] ideal_dout_out; 1519 wire valid_i; 1520 wire valid_out; 1521 wire underflow_i; 1522 1523 //Ideal FIFO signals. These are the raw output of the behavioral model, 1524 //which behaves like an ideal FIFO. 1525 reg [1:0] err_type = 0; 1526 reg [1:0] err_type_d1 = 0; 1527 reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; 1528 reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; 1529 reg ideal_wr_ack = 0; 1530 reg ideal_valid = 0; 1531 reg ideal_overflow = 0; 1532 reg ideal_underflow = 0; 1533 reg ideal_prog_full = 0; 1534 reg ideal_prog_empty = 1; 1535 reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; 1536 reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; 1537 1538 //Assorted reg values for delayed versions of signals 1539 reg valid_d1 = 0; 1540 1541 1542 //user specified value for reseting the size of the fifo 1543 reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; 1544 1545 //temporary registers for WR_RESPONSE_LATENCY feature 1546 1547 integer tmp_wr_listsize; 1548 integer tmp_rd_listsize; 1549 1550 //Signal for registered version of prog full and empty 1551 1552 //Threshold values for Programmable Flags 1553 integer prog_empty_actual_thresh_assert; 1554 integer prog_empty_actual_thresh_negate; 1555 integer prog_full_actual_thresh_assert; 1556 integer prog_full_actual_thresh_negate; 1557 1558 1559 /**************************************************************************** 1560 * Function Declarations 1561 ***************************************************************************/ 1562 1563 /************************************************************************** 1564 * write_fifo 1565 * This task writes a word to the FIFO memory and updates the 1566 * write pointer. 1567 * FIFO size is relative to write domain. 1568 ***************************************************************************/ 1569 task write_fifo; 1570 begin 1571 memory[wr_ptr] <= DIN; 1572 wr_pntr <= #`TCQ wr_pntr + 1; 1573 // Store the type of error injection (double/single) on write 1574 case (C_ERROR_INJECTION_TYPE) 1575 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; 1576 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; 1577 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; 1578 default: ecc_err[wr_ptr] <= 0; 1579 endcase 1580 // (Works opposite to core: wr_ptr is a DOWN counter) 1581 if (wr_ptr == 0) begin 1582 wr_ptr <= C_WR_DEPTH - 1; 1583 end else begin 1584 wr_ptr <= wr_ptr - 1; 1585 end 1586 end 1587 endtask // write_fifo 1588 1589 /************************************************************************** 1590 * read_fifo 1591 * This task reads a word from the FIFO memory and updates the read 1592 * pointer. It's output is the ideal_dout bus. 1593 * FIFO size is relative to write domain. 1594 ***************************************************************************/ 1595 task read_fifo; 1596 integer i; 1597 reg [C_DOUT_WIDTH-1:0] tmp_dout; 1598 reg [C_DIN_WIDTH-1:0] memory_read; 1599 reg [31:0] tmp_rd_ptr; 1600 reg [31:0] rd_ptr_high; 1601 reg [31:0] rd_ptr_low; 1602 reg [1:0] tmp_ecc_err; 1603 begin 1604 rd_pntr <= #`TCQ rd_pntr + 1; 1605 // output is wider than input 1606 if (reads_per_write == 0) begin 1607 tmp_dout = 0; 1608 tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); 1609 for (i = writes_per_read - 1; i >= 0; i = i - 1) begin 1610 tmp_dout = tmp_dout << C_DIN_WIDTH; 1611 tmp_dout = tmp_dout | memory[tmp_rd_ptr]; 1612 1613 // (Works opposite to core: rd_ptr is a DOWN counter) 1614 if (tmp_rd_ptr == 0) begin 1615 tmp_rd_ptr = C_WR_DEPTH - 1; 1616 end else begin 1617 tmp_rd_ptr = tmp_rd_ptr - 1; 1618 end 1619 end 1620 1621 // output is symmetric 1622 end else if (reads_per_write == 1) begin 1623 tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; 1624 // Retreive the error injection type. Based on the error injection type 1625 // corrupt the output data. 1626 tmp_ecc_err = ecc_err[rd_ptr]; 1627 if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin 1628 if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error 1629 if (C_DOUT_WIDTH == 1) 1630 tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; 1631 else if (C_DOUT_WIDTH == 2) 1632 tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; 1633 else 1634 tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; 1635 end else begin 1636 tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; 1637 end 1638 err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; 1639 end else begin 1640 err_type <= 0; 1641 end 1642 1643 // input is wider than output 1644 end else begin 1645 rd_ptr_high = rd_ptr >> log2_reads_per_write; 1646 rd_ptr_low = rd_ptr & (reads_per_write - 1); 1647 memory_read = memory[rd_ptr_high]; 1648 tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); 1649 end 1650 ideal_dout <= tmp_dout; 1651 1652 // (Works opposite to core: rd_ptr is a DOWN counter) 1653 if (rd_ptr == 0) begin 1654 rd_ptr <= C_RD_DEPTH - 1; 1655 end else begin 1656 rd_ptr <= rd_ptr - 1; 1657 end 1658 end 1659 endtask 1660 1661 /************************************************************************** 1662 * log2_val 1663 * Returns the 'log2' value for the input value for the supported ratios 1664 ***************************************************************************/ 1665 function [31:0] log2_val; 1666 input [31:0] binary_val; 1667 1668 begin 1669 if (binary_val == 8) begin 1670 log2_val = 3; 1671 end else if (binary_val == 4) begin 1672 log2_val = 2; 1673 end else begin 1674 log2_val = 1; 1675 end 1676 end 1677 endfunction 1678 1679 /*********************************************************************** 1680 * hexstr_conv 1681 * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) 1682 ***********************************************************************/ 1683 function [C_DOUT_WIDTH-1:0] hexstr_conv; 1684 input [(C_DOUT_WIDTH*8)-1:0] def_data; 1685 1686 integer index,i,j; 1687 reg [3:0] bin; 1688 1689 begin 1690 index = 0; 1691 hexstr_conv = 'b0; 1692 for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) 1693 begin 1694 case (def_data[7:0]) 1695 8'b00000000 : 1696 begin 1697 bin = 4'b0000; 1698 i = -1; 1699 end 1700 8'b00110000 : bin = 4'b0000; 1701 8'b00110001 : bin = 4'b0001; 1702 8'b00110010 : bin = 4'b0010; 1703 8'b00110011 : bin = 4'b0011; 1704 8'b00110100 : bin = 4'b0100; 1705 8'b00110101 : bin = 4'b0101; 1706 8'b00110110 : bin = 4'b0110; 1707 8'b00110111 : bin = 4'b0111; 1708 8'b00111000 : bin = 4'b1000; 1709 8'b00111001 : bin = 4'b1001; 1710 8'b01000001 : bin = 4'b1010; 1711 8'b01000010 : bin = 4'b1011; 1712 8'b01000011 : bin = 4'b1100; 1713 8'b01000100 : bin = 4'b1101; 1714 8'b01000101 : bin = 4'b1110; 1715 8'b01000110 : bin = 4'b1111; 1716 8'b01100001 : bin = 4'b1010; 1717 8'b01100010 : bin = 4'b1011; 1718 8'b01100011 : bin = 4'b1100; 1719 8'b01100100 : bin = 4'b1101; 1720 8'b01100101 : bin = 4'b1110; 1721 8'b01100110 : bin = 4'b1111; 1722 default : 1723 begin 1724 bin = 4'bx; 1725 end 1726 endcase 1727 for( j=0; j<4; j=j+1) 1728 begin 1729 if ((index*4)+j < C_DOUT_WIDTH) 1730 begin 1731 hexstr_conv[(index*4)+j] = bin[j]; 1732 end 1733 end 1734 index = index + 1; 1735 def_data = def_data >> 8; 1736 end 1737 end 1738 endfunction 1739 1740 /************************************************************************* 1741 * Initialize Signals for clean power-on simulation 1742 *************************************************************************/ 1743 initial begin 1744 num_wr_bits = 0; 1745 num_rd_bits = 0; 1746 next_num_wr_bits = 0; 1747 next_num_rd_bits = 0; 1748 rd_ptr = C_RD_DEPTH - 1; 1749 wr_ptr = C_WR_DEPTH - 1; 1750 wr_pntr = 0; 1751 rd_pntr = 0; 1752 rd_ptr_wrclk = rd_ptr; 1753 wr_ptr_rdclk = wr_ptr; 1754 dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); 1755 ideal_dout = dout_reset_val; 1756 err_type = 0; 1757 ideal_dout_d1 = dout_reset_val; 1758 ideal_wr_ack = 1'b0; 1759 ideal_valid = 1'b0; 1760 valid_d1 = 1'b0; 1761 ideal_overflow = 1'b0; 1762 ideal_underflow = 1'b0; 1763 ideal_wr_count = 0; 1764 ideal_rd_count = 0; 1765 ideal_prog_full = 1'b0; 1766 ideal_prog_empty = 1'b1; 1767 end 1768 1769 1770 /************************************************************************* 1771 * Connect the module inputs and outputs to the internal signals of the 1772 * behavioral model. 1773 *************************************************************************/ 1774 //Inputs 1775 /* 1776 wire [C_DIN_WIDTH-1:0] DIN; 1777 wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; 1778 wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; 1779 wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; 1780 wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; 1781 wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; 1782 wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; 1783 wire RD_CLK; 1784 wire RD_EN; 1785 wire RST; 1786 wire WR_CLK; 1787 wire WR_EN; 1788 */ 1789 1790 //*************************************************************************** 1791 // Dout may change behavior based on latency 1792 //*************************************************************************** 1793 assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && 1794 (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? 1795 ideal_dout_d1: ideal_dout; 1796 assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; 1797 1798 //*************************************************************************** 1799 // Assign SBITERR and DBITERR based on latency 1800 //*************************************************************************** 1801 assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && 1802 (C_PRELOAD_LATENCY == 2 && 1803 (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? 1804 err_type_d1[0]: err_type[0]; 1805 assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && 1806 (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? 1807 err_type_d1[1]: err_type[1]; 1808 1809 1810 //*************************************************************************** 1811 // Overflow may be active-low 1812 //*************************************************************************** 1813 generate 1814 if (C_HAS_OVERFLOW==1) begin : blockOF1 1815 assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; 1816 end 1817 endgenerate 1818 1819 assign PROG_EMPTY = ideal_prog_empty; 1820 assign PROG_FULL = ideal_prog_full; 1821 1822 //*************************************************************************** 1823 // Valid may change behavior based on latency or active-low 1824 //*************************************************************************** 1825 generate 1826 if (C_HAS_VALID==1) begin : blockVL1 1827 assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; 1828 assign valid_out = (C_PRELOAD_LATENCY==2 && 1829 (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? 1830 valid_d1: valid_i; 1831 assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; 1832 end 1833 endgenerate 1834 1835 1836 //*************************************************************************** 1837 // Underflow may change behavior based on latency or active-low 1838 //*************************************************************************** 1839 generate 1840 if (C_HAS_UNDERFLOW==1) begin : blockUF1 1841 assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; 1842 assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; 1843 end 1844 endgenerate 1845 1846 //*************************************************************************** 1847 // Write acknowledge may be active low 1848 //*************************************************************************** 1849 generate 1850 if (C_HAS_WR_ACK==1) begin : blockWK1 1851 assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; 1852 end 1853 endgenerate 1854 1855 1856 //*************************************************************************** 1857 // Generate RD_DATA_COUNT if Use Extra Logic option is selected 1858 //*************************************************************************** 1859 generate 1860 if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext 1861 1862 reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0; 1863 reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0; 1864 wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp; 1865 wire [C_PNTR_WIDTH:0] diff_wr_rd; 1866 reg [C_PNTR_WIDTH:0] wr_data_count_i = 0; 1867 always @* begin 1868 if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin 1869 adjusted_wr_pntr = wr_pntr; 1870 adjusted_rd_pntr = 0; 1871 adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; 1872 end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin 1873 adjusted_rd_pntr = rd_pntr_wr; 1874 adjusted_wr_pntr = 0; 1875 adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; 1876 end else begin 1877 adjusted_wr_pntr = wr_pntr; 1878 adjusted_rd_pntr = rd_pntr_wr; 1879 end 1880 end // always @* 1881 1882 assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr; 1883 assign diff_wr_rd = {1'b0,diff_wr_rd_tmp}; 1884 1885 always @ (posedge wr_rst_i or posedge WR_CLK) 1886 begin 1887 if (wr_rst_i) 1888 wr_data_count_i <= #`TCQ 0; 1889 else 1890 wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC; 1891 end // always @ (posedge WR_CLK or posedge WR_CLK) 1892 1893 always @* begin 1894 if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) 1895 wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0]; 1896 else 1897 wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; 1898 end // always @* 1899 end // wdc_fwft_ext 1900 endgenerate 1901 1902 //*************************************************************************** 1903 // Generate RD_DATA_COUNT if Use Extra Logic option is selected 1904 //*************************************************************************** 1905 reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0; 1906 1907 generate 1908 if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext 1909 reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; 1910 wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; 1911 wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; 1912 always @* begin 1913 if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin 1914 adjusted_wr_pntr_rd = 0; 1915 adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; 1916 end else begin 1917 adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; 1918 end 1919 end // always @* 1920 1921 assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; 1922 assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; 1923 1924 always @ (posedge rd_rst_i or posedge RD_CLK) 1925 begin 1926 if (rd_rst_i) begin 1927 rdc_fwft_ext_as <= #`TCQ 0; 1928 end else begin 1929 if (!stage2_valid) 1930 rdc_fwft_ext_as <= #`TCQ 0; 1931 else if (!stage1_valid && stage2_valid) 1932 rdc_fwft_ext_as <= #`TCQ 1; 1933 else 1934 rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2; 1935 end 1936 end // always @ (posedge WR_CLK or posedge WR_CLK) 1937 end // rdc_fwft_ext 1938 endgenerate 1939 1940 //*************************************************************************** 1941 // Assign the read data count value only if it is selected, 1942 // otherwise output zeros. 1943 //*************************************************************************** 1944 generate 1945 if (C_HAS_RD_DATA_COUNT == 1) begin : grdc 1946 assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ? 1947 rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] : 1948 rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; 1949 end 1950 endgenerate 1951 1952 generate 1953 if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc 1954 assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH-1{1'b0}}; 1955 end 1956 endgenerate 1957 1958 //*************************************************************************** 1959 // Assign the write data count value only if it is selected, 1960 // otherwise output zeros 1961 //*************************************************************************** 1962 generate 1963 if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc 1964 assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ? 1965 wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] : 1966 wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH]; 1967 end 1968 endgenerate 1969 1970 generate 1971 if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc 1972 assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; 1973 end 1974 endgenerate 1975 1976 1977 /************************************************************************** 1978 * Assorted registers for delayed versions of signals 1979 **************************************************************************/ 1980 //Capture delayed version of valid 1981 generate 1982 if (C_HAS_VALID==1) begin : blockVL2 1983 always @(posedge RD_CLK or posedge rd_rst_i) begin 1984 if (rd_rst_i == 1'b1) begin 1985 valid_d1 <= #`TCQ 1'b0; 1986 end else begin 1987 valid_d1 <= #`TCQ valid_i; 1988 end 1989 end 1990 end 1991 endgenerate 1992 1993 //Capture delayed version of dout 1994 always @(posedge RD_CLK or posedge rd_rst_i) begin 1995 if (rd_rst_i == 1'b1) begin 1996 // Reset err_type only if ECC is not selected 1997 if (C_USE_ECC == 0) 1998 err_type_d1 <= #`TCQ 0; 1999 end else if (ram_rd_en_d1) begin 2000 ideal_dout_d1 <= #`TCQ ideal_dout; 2001 err_type_d1 <= #`TCQ err_type; 2002 end 2003 end 2004 2005 /************************************************************************** 2006 * Overflow and Underflow Flag calculation 2007 * (handled separately because they don't support rst) 2008 **************************************************************************/ 2009 generate 2010 if (C_HAS_OVERFLOW==1) begin : blockOF2 2011 always @(posedge WR_CLK) begin 2012 ideal_overflow <= #`TCQ WR_EN & FULL; 2013 end 2014 end 2015 endgenerate 2016 2017 generate 2018 if (C_HAS_UNDERFLOW==1) begin : blockUF2 2019 always @(posedge RD_CLK) begin 2020 ideal_underflow <= #`TCQ EMPTY & RD_EN; 2021 end 2022 end 2023 endgenerate 2024 2025 /************************************************************************** 2026 * Write Domain Logic 2027 **************************************************************************/ 2028 reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; 2029 always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w 2030 2031 /****** Reset fifo (case 1)***************************************/ 2032 if (wr_rst_i == 1'b1) begin 2033 num_wr_bits <= #`TCQ 0; 2034 next_num_wr_bits = #`TCQ 0; 2035 wr_ptr <= #`TCQ C_WR_DEPTH - 1; 2036 rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; 2037 ideal_wr_ack <= #`TCQ 0; 2038 ideal_wr_count <= #`TCQ 0; 2039 tmp_wr_listsize = #`TCQ 0; 2040 rd_ptr_wrclk_next <= #`TCQ 0; 2041 wr_pntr <= #`TCQ 0; 2042 wr_pntr_rd1 <= #`TCQ 0; 2043 rd_pntr_wr2 <= #`TCQ 0; 2044 rd_pntr_wr3 <= #`TCQ 0; 2045 rd_pntr_wr4 <= #`TCQ 0; 2046 rd_pntr_wr <= #`TCQ 0; 2047 2048 2049 end else begin //wr_rst_i==0 2050 2051 wr_pntr_rd1 <= #`TCQ wr_pntr; 2052 2053 // Synchronize the rd_pntr in read domain 2054 rd_pntr_wr2 <= #`TCQ rd_pntr_wr1; 2055 rd_pntr_wr3 <= #`TCQ rd_pntr_wr2; 2056 rd_pntr_wr4 <= #`TCQ rd_pntr_wr2; 2057 rd_pntr_wr <= #`TCQ rd_pntr_wr4; 2058 2059 2060 2061 //Determine the current number of words in the FIFO 2062 tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : 2063 num_wr_bits/C_DIN_WIDTH; 2064 rd_ptr_wrclk_next = rd_ptr; 2065 if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin 2066 next_num_wr_bits = num_wr_bits - 2067 C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH 2068 - rd_ptr_wrclk_next); 2069 end else begin 2070 next_num_wr_bits = num_wr_bits - 2071 C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); 2072 end 2073 2074 //If this is a write, handle the write by adding the value 2075 // to the linked list, and updating all outputs appropriately 2076 if (WR_EN == 1'b1) begin 2077 if (FULL == 1'b1) begin 2078 2079 //If the FIFO is full, do NOT perform the write, 2080 // update flags accordingly 2081 if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD 2082 >= C_FIFO_WR_DEPTH) begin 2083 //write unsuccessful - do not change contents 2084 2085 //Do not acknowledge the write 2086 ideal_wr_ack <= #`TCQ 0; 2087 //Reminder that FIFO is still full 2088 2089 ideal_wr_count <= #`TCQ num_write_words_sized_i; 2090 2091 //If the FIFO is one from full, but reporting full 2092 end else 2093 if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == 2094 C_FIFO_WR_DEPTH-1) begin 2095 //No change to FIFO 2096 2097 //Write not successful 2098 ideal_wr_ack <= #`TCQ 0; 2099 //With DEPTH-1 words in the FIFO, it is almost_full 2100 2101 ideal_wr_count <= #`TCQ num_write_words_sized_i; 2102 2103 2104 //If the FIFO is completely empty, but it is 2105 // reporting FULL for some reason (like reset) 2106 end else 2107 if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= 2108 C_FIFO_WR_DEPTH-2) begin 2109 //No change to FIFO 2110 2111 //Write not successful 2112 ideal_wr_ack <= #`TCQ 0; 2113 //FIFO is really not close to full, so change flag status. 2114 2115 ideal_wr_count <= #`TCQ num_write_words_sized_i; 2116 end //(tmp_wr_listsize == 0) 2117 2118 end else begin 2119 2120 //If the FIFO is full, do NOT perform the write, 2121 // update flags accordingly 2122 if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= 2123 C_FIFO_WR_DEPTH) begin 2124 //write unsuccessful - do not change contents 2125 2126 //Do not acknowledge the write 2127 ideal_wr_ack <= #`TCQ 0; 2128 //Reminder that FIFO is still full 2129 2130 ideal_wr_count <= #`TCQ num_write_words_sized_i; 2131 2132 //If the FIFO is one from full 2133 end else 2134 if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == 2135 C_FIFO_WR_DEPTH-1) begin 2136 //Add value on DIN port to FIFO 2137 write_fifo; 2138 next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; 2139 2140 //Write successful, so issue acknowledge 2141 // and no error 2142 ideal_wr_ack <= #`TCQ 1; 2143 //This write is CAUSING the FIFO to go full 2144 2145 ideal_wr_count <= #`TCQ num_write_words_sized_i; 2146 2147 //If the FIFO is 2 from full 2148 end else 2149 if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == 2150 C_FIFO_WR_DEPTH-2) begin 2151 //Add value on DIN port to FIFO 2152 write_fifo; 2153 next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; 2154 //Write successful, so issue acknowledge 2155 // and no error 2156 ideal_wr_ack <= #`TCQ 1; 2157 //Still 2 from full 2158 2159 ideal_wr_count <= #`TCQ num_write_words_sized_i; 2160 2161 //If the FIFO is not close to being full 2162 end else 2163 if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < 2164 C_FIFO_WR_DEPTH-2) begin 2165 //Add value on DIN port to FIFO 2166 write_fifo; 2167 next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; 2168 //Write successful, so issue acknowledge 2169 // and no error 2170 ideal_wr_ack <= #`TCQ 1; 2171 //Not even close to full. 2172 2173 ideal_wr_count <= num_write_words_sized_i; 2174 2175 end 2176 2177 end 2178 2179 end else begin //(WR_EN == 1'b1) 2180 2181 //If user did not attempt a write, then do not 2182 // give ack or err 2183 ideal_wr_ack <= #`TCQ 0; 2184 ideal_wr_count <= #`TCQ num_write_words_sized_i; 2185 end 2186 num_wr_bits <= #`TCQ next_num_wr_bits; 2187 rd_ptr_wrclk <= #`TCQ rd_ptr; 2188 2189 end //wr_rst_i==0 2190 end // write always 2191 2192 2193 /*************************************************************************** 2194 * Programmable FULL flags 2195 ***************************************************************************/ 2196 2197 always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf 2198 2199 if (RST_FULL_FF == 1'b1) begin 2200 diff_pntr <= 0; 2201 ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; 2202 end else begin 2203 if (ram_wr_en) 2204 diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1); 2205 else if (!ram_wr_en) 2206 diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr); 2207 2208 if (RST_FULL_GEN) 2209 ideal_prog_full <= #`TCQ 0; 2210 //Single Programmable Full Constant Threshold 2211 else if (C_PROG_FULL_TYPE == 1) begin 2212 if (FULL == 0) begin 2213 if (diff_pntr >= C_PROG_FULL_THRESH_ASSERT_VAL) 2214 ideal_prog_full <= #`TCQ 1; 2215 else 2216 ideal_prog_full <= #`TCQ 0; 2217 end else 2218 ideal_prog_full <= #`TCQ ideal_prog_full; 2219 //Two Programmable Full Constant Thresholds 2220 end else if (C_PROG_FULL_TYPE == 2) begin 2221 if (FULL == 0) begin 2222 if (diff_pntr >= C_PROG_FULL_THRESH_ASSERT_VAL) 2223 ideal_prog_full <= #`TCQ 1; 2224 else if (diff_pntr < C_PROG_FULL_THRESH_NEGATE_VAL) 2225 ideal_prog_full <= #`TCQ 0; 2226 else 2227 ideal_prog_full <= #`TCQ ideal_prog_full; 2228 end else 2229 ideal_prog_full <= #`TCQ ideal_prog_full; 2230 //Single Programmable Full Threshold Input 2231 end else if (C_PROG_FULL_TYPE == 3) begin 2232 if (FULL == 0) begin 2233 if (diff_pntr >= PROG_FULL_THRESH) 2234 ideal_prog_full <= #`TCQ 1; 2235 else 2236 ideal_prog_full <= #`TCQ 0; 2237 end else 2238 ideal_prog_full <= #`TCQ ideal_prog_full; 2239 //Two Programmable Full Threshold Inputs 2240 end else if (C_PROG_FULL_TYPE == 4) begin 2241 if (FULL == 0) begin 2242 if (diff_pntr >= PROG_FULL_THRESH_ASSERT) 2243 ideal_prog_full <= #`TCQ 1; 2244 else if (diff_pntr < PROG_FULL_THRESH_NEGATE) 2245 ideal_prog_full <= #`TCQ 0; 2246 else 2247 ideal_prog_full <= #`TCQ ideal_prog_full; 2248 end else 2249 ideal_prog_full <= #`TCQ ideal_prog_full; 2250 end // C_PROG_FULL_TYPE 2251 2252 end //wr_rst_i==0 2253 end // 2254 2255 2256 /************************************************************************** 2257 * Read Domain Logic 2258 **************************************************************************/ 2259 2260 2261 /********************************************************* 2262 * Programmable EMPTY flags 2263 *********************************************************/ 2264 //Determine the Assert and Negate thresholds for Programmable Empty 2265 2266 reg [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val = 0; 2267 reg [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val = 0; 2268 reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0; 2269 always @* begin 2270 2271 if (C_PROG_EMPTY_TYPE == 3) begin 2272 2273 // If empty input threshold is selected, then subtract 2 for FWFT to 2274 // compensate the FWFT stage, otherwise assign the input value. 2275 if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) // FWFT 2276 pe_thr_assert_val <= PROG_EMPTY_THRESH - 2'h2; 2277 else 2278 pe_thr_assert_val <= PROG_EMPTY_THRESH; 2279 2280 end else if (C_PROG_EMPTY_TYPE == 4) begin 2281 2282 // If empty input threshold is selected, then subtract 2 for FWFT to 2283 // compensate the FWFT stage, otherwise assign the input value. 2284 if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT 2285 pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT - 2'h2; 2286 pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE - 2'h2; 2287 end else begin 2288 pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT; 2289 pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE; 2290 end 2291 end else begin 2292 2293 if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT 2294 pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL - 2; 2295 pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL - 2; 2296 end else begin 2297 pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL; 2298 pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL; 2299 end 2300 end 2301 end // always @* 2302 2303 always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe 2304 2305 if (rd_rst_i) begin 2306 diff_pntr_rd <= #`TCQ 0; 2307 ideal_prog_empty <= #`TCQ 1'b1; 2308 end else begin 2309 if (ram_rd_en) 2310 diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1; 2311 else if (!ram_rd_en) 2312 diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr); 2313 else 2314 diff_pntr_rd <= #`TCQ diff_pntr_rd; 2315 2316 if (C_PROG_EMPTY_TYPE == 1) begin 2317 if (EMPTY == 0) begin 2318 if (diff_pntr_rd <= pe_thr_assert_val) 2319 ideal_prog_empty <= #`TCQ 1; 2320 else 2321 ideal_prog_empty <= #`TCQ 0; 2322 end else 2323 ideal_prog_empty <= #`TCQ ideal_prog_empty; 2324 end else if (C_PROG_EMPTY_TYPE == 2) begin 2325 if (EMPTY == 0) begin 2326 if (diff_pntr_rd <= pe_thr_assert_val) 2327 ideal_prog_empty <= #`TCQ 1; 2328 else if (diff_pntr_rd > pe_thr_negate_val) 2329 ideal_prog_empty <= #`TCQ 0; 2330 else 2331 ideal_prog_empty <= #`TCQ ideal_prog_empty; 2332 end else 2333 ideal_prog_empty <= #`TCQ ideal_prog_empty; 2334 end else if (C_PROG_EMPTY_TYPE == 3) begin 2335 if (EMPTY == 0) begin 2336 if (diff_pntr_rd <= pe_thr_assert_val) 2337 ideal_prog_empty <= #`TCQ 1; 2338 else 2339 ideal_prog_empty <= #`TCQ 0; 2340 end else 2341 ideal_prog_empty <= #`TCQ ideal_prog_empty; 2342 end else if (C_PROG_EMPTY_TYPE == 4) begin 2343 if (EMPTY == 0) begin 2344 if (diff_pntr_rd >= pe_thr_assert_val) 2345 ideal_prog_empty <= #`TCQ 1; 2346 else if (diff_pntr_rd > pe_thr_negate_val) 2347 ideal_prog_empty <= #`TCQ 0; 2348 else 2349 ideal_prog_empty <= #`TCQ ideal_prog_empty; 2350 end else 2351 ideal_prog_empty <= #`TCQ ideal_prog_empty; 2352 end //C_PROG_EMPTY_TYPE 2353 end 2354 end 2355 2356 // block memory has a synchronous reset 2357 always @(posedge RD_CLK) begin : gen_fifo_blkmemdout 2358 // make it consistent with the core. 2359 if (rd_rst_i) begin 2360 // Reset err_type only if ECC is not selected 2361 if (C_USE_ECC == 0 && C_MEMORY_TYPE < 2) 2362 err_type <= #`TCQ 0; 2363 2364 // BRAM resets synchronously 2365 if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin 2366 ideal_dout <= #`TCQ dout_reset_val; 2367 ideal_dout_d1 <= #`TCQ dout_reset_val; 2368 end 2369 end 2370 end //always 2371 2372 always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r 2373 2374 /****** Reset fifo (case 1)***************************************/ 2375 if (rd_rst_i) begin 2376 num_rd_bits <= #`TCQ 0; 2377 next_num_rd_bits = #`TCQ 0; 2378 rd_ptr <= #`TCQ C_RD_DEPTH -1; 2379 rd_pntr <= #`TCQ 0; 2380 rd_pntr_wr1 <= #`TCQ 0; 2381 wr_pntr_rd2 <= #`TCQ 0; 2382 wr_pntr_rd3 <= #`TCQ 0; 2383 wr_pntr_rd <= #`TCQ 0; 2384 wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; 2385 2386 // DRAM resets asynchronously 2387 if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) 2388 ideal_dout <= #`TCQ dout_reset_val; 2389 2390 // Reset err_type only if ECC is not selected 2391 if (C_USE_ECC == 0) 2392 err_type <= #`TCQ 0; 2393 ideal_valid <= #`TCQ 1'b0; 2394 ideal_rd_count <= #`TCQ 0; 2395 2396 end else begin //rd_rst_i==0 2397 2398 rd_pntr_wr1 <= #`TCQ rd_pntr; 2399 2400 // Synchronize the wr_pntr in read domain 2401 wr_pntr_rd2 <= #`TCQ wr_pntr_rd1; 2402 wr_pntr_rd3 <= #`TCQ wr_pntr_rd2; 2403 wr_pntr_rd <= #`TCQ wr_pntr_rd3; 2404 2405 2406 2407 //Determine the current number of words in the FIFO 2408 tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : 2409 num_rd_bits/C_DOUT_WIDTH; 2410 wr_ptr_rdclk_next = wr_ptr; 2411 2412 if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin 2413 next_num_rd_bits = num_rd_bits + 2414 C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH 2415 - wr_ptr_rdclk_next); 2416 end else begin 2417 next_num_rd_bits = num_rd_bits + 2418 C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); 2419 end 2420 2421 /*****************************************************************/ 2422 // Read Operation - Read Latency 1 2423 /*****************************************************************/ 2424 if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin 2425 ideal_valid <= #`TCQ 1'b0; 2426 2427 if (ram_rd_en == 1'b1) begin 2428 2429 if (EMPTY == 1'b1) begin 2430 2431 //If the FIFO is completely empty, and is reporting empty 2432 if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) 2433 begin 2434 //Do not change the contents of the FIFO 2435 2436 //Do not acknowledge the read from empty FIFO 2437 ideal_valid <= #`TCQ 1'b0; 2438 //Reminder that FIFO is still empty 2439 2440 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2441 end // if (tmp_rd_listsize <= 0) 2442 2443 //If the FIFO is one from empty, but it is reporting empty 2444 else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) 2445 begin 2446 //Do not change the contents of the FIFO 2447 2448 //Do not acknowledge the read from empty FIFO 2449 ideal_valid <= #`TCQ 1'b0; 2450 //Note that FIFO is no longer empty, but is almost empty (has one word left) 2451 2452 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2453 2454 end // if (tmp_rd_listsize == 1) 2455 2456 //If the FIFO is two from empty, and is reporting empty 2457 else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) 2458 begin 2459 //Do not change the contents of the FIFO 2460 2461 //Do not acknowledge the read from empty FIFO 2462 ideal_valid <= #`TCQ 1'b0; 2463 //Fifo has two words, so is neither empty or almost empty 2464 2465 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2466 2467 end // if (tmp_rd_listsize == 2) 2468 2469 //If the FIFO is not close to empty, but is reporting that it is 2470 // Treat the FIFO as empty this time, but unset EMPTY flags. 2471 if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) 2472 begin 2473 //Do not change the contents of the FIFO 2474 2475 //Do not acknowledge the read from empty FIFO 2476 ideal_valid <= #`TCQ 1'b0; 2477 //Note that the FIFO is No Longer Empty or Almost Empty 2478 2479 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2480 2481 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) 2482 end // else: if(ideal_empty == 1'b1) 2483 2484 else //if (ideal_empty == 1'b0) 2485 begin 2486 2487 //If the FIFO is completely full, and we are successfully reading from it 2488 if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) 2489 begin 2490 //Read the value from the FIFO 2491 read_fifo; 2492 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 2493 2494 //Acknowledge the read from the FIFO, no error 2495 ideal_valid <= #`TCQ 1'b1; 2496 //Not close to empty 2497 2498 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2499 2500 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) 2501 2502 //If the FIFO is not close to being empty 2503 else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) 2504 begin 2505 //Read the value from the FIFO 2506 read_fifo; 2507 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 2508 2509 //Acknowledge the read from the FIFO, no error 2510 ideal_valid <= #`TCQ 1'b1; 2511 //Not close to empty 2512 2513 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2514 2515 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) 2516 2517 //If the FIFO is two from empty 2518 else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) 2519 begin 2520 //Read the value from the FIFO 2521 read_fifo; 2522 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 2523 2524 //Acknowledge the read from the FIFO, no error 2525 ideal_valid <= #`TCQ 1'b1; 2526 //Fifo is not yet empty. It is going almost_empty 2527 2528 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2529 2530 end // if (tmp_rd_listsize == 2) 2531 2532 //If the FIFO is one from empty 2533 else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) 2534 begin 2535 //Read the value from the FIFO 2536 read_fifo; 2537 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 2538 2539 //Acknowledge the read from the FIFO, no error 2540 ideal_valid <= #`TCQ 1'b1; 2541 //Note that FIFO is GOING empty 2542 2543 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2544 2545 end // if (tmp_rd_listsize == 1) 2546 2547 2548 //If the FIFO is completely empty 2549 else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) 2550 begin 2551 //Do not change the contents of the FIFO 2552 2553 //Do not acknowledge the read from empty FIFO 2554 ideal_valid <= #`TCQ 1'b0; 2555 2556 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2557 2558 end // if (tmp_rd_listsize <= 0) 2559 2560 end // if (ideal_empty == 1'b0) 2561 2562 end //(RD_EN == 1'b1) 2563 2564 else //if (RD_EN == 1'b0) 2565 begin 2566 //If user did not attempt a read, do not give an ack or err 2567 ideal_valid <= #`TCQ 1'b0; 2568 2569 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2570 2571 end // else: !if(RD_EN == 1'b1) 2572 2573 /*****************************************************************/ 2574 // Read Operation - Read Latency 0 2575 /*****************************************************************/ 2576 end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin 2577 ideal_valid <= #`TCQ 1'b0; 2578 if (ram_rd_en == 1'b1) begin 2579 2580 if (EMPTY == 1'b1) begin 2581 2582 //If the FIFO is completely empty, and is reporting empty 2583 if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin 2584 //Do not change the contents of the FIFO 2585 2586 //Do not acknowledge the read from empty FIFO 2587 ideal_valid <= #`TCQ 1'b0; 2588 //Reminder that FIFO is still empty 2589 2590 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2591 2592 //If the FIFO is one from empty, but it is reporting empty 2593 end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin 2594 //Do not change the contents of the FIFO 2595 2596 //Do not acknowledge the read from empty FIFO 2597 ideal_valid <= #`TCQ 1'b0; 2598 //Note that FIFO is no longer empty, but is almost empty (has one word left) 2599 2600 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2601 2602 //If the FIFO is two from empty, and is reporting empty 2603 end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin 2604 //Do not change the contents of the FIFO 2605 2606 //Do not acknowledge the read from empty FIFO 2607 ideal_valid <= #`TCQ 1'b0; 2608 //Fifo has two words, so is neither empty or almost empty 2609 2610 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2611 2612 //If the FIFO is not close to empty, but is reporting that it is 2613 // Treat the FIFO as empty this time, but unset EMPTY flags. 2614 end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && 2615 (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin 2616 //Do not change the contents of the FIFO 2617 2618 //Do not acknowledge the read from empty FIFO 2619 ideal_valid <= #`TCQ 1'b0; 2620 //Note that the FIFO is No Longer Empty or Almost Empty 2621 2622 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2623 2624 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) 2625 2626 end else begin 2627 2628 //If the FIFO is completely full, and we are successfully reading from it 2629 if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin 2630 //Read the value from the FIFO 2631 read_fifo; 2632 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 2633 2634 //Acknowledge the read from the FIFO, no error 2635 ideal_valid <= #`TCQ 1'b1; 2636 //Not close to empty 2637 2638 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2639 2640 //If the FIFO is not close to being empty 2641 end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && 2642 (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin 2643 //Read the value from the FIFO 2644 read_fifo; 2645 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 2646 2647 //Acknowledge the read from the FIFO, no error 2648 ideal_valid <= #`TCQ 1'b1; 2649 //Not close to empty 2650 2651 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2652 2653 //If the FIFO is two from empty 2654 end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin 2655 //Read the value from the FIFO 2656 read_fifo; 2657 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 2658 2659 //Acknowledge the read from the FIFO, no error 2660 ideal_valid <= #`TCQ 1'b1; 2661 //Fifo is not yet empty. It is going almost_empty 2662 2663 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2664 2665 //If the FIFO is one from empty 2666 end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin 2667 //Read the value from the FIFO 2668 read_fifo; 2669 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; 2670 2671 //Acknowledge the read from the FIFO, no error 2672 ideal_valid <= #`TCQ 1'b1; 2673 //Note that FIFO is GOING empty 2674 2675 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2676 2677 //If the FIFO is completely empty 2678 end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin 2679 //Do not change the contents of the FIFO 2680 2681 //Do not acknowledge the read from empty FIFO 2682 ideal_valid <= #`TCQ 1'b0; 2683 //Reminder that FIFO is still empty 2684 2685 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2686 2687 end // if (tmp_rd_listsize <= 0) 2688 2689 end // if (ideal_empty == 1'b0) 2690 2691 end else begin//(RD_EN == 1'b0) 2692 2693 2694 //If user did not attempt a read, do not give an ack or err 2695 ideal_valid <= #`TCQ 1'b0; 2696 ideal_rd_count <= #`TCQ num_read_words_sized_i; 2697 2698 end // else: !if(RD_EN == 1'b1) 2699 end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) 2700 2701 num_rd_bits <= #`TCQ next_num_rd_bits; 2702 wr_ptr_rdclk <= #`TCQ wr_ptr; 2703 end //rd_rst_i==0 2704 end //always 2705 2706endmodule // fifo_generator_v6_1_bhv_ver_as 2707 2708 2709/******************************************************************************* 2710 * Declaration of top-level module 2711 ******************************************************************************/ 2712module fifo_generator_v6_1_bhv_ver_ss 2713 2714 /************************************************************************** 2715 * Declare user parameters and their defaults 2716 *************************************************************************/ 2717 #( 2718 parameter C_DATA_COUNT_WIDTH = 2, 2719 parameter C_DIN_WIDTH = 8, 2720 parameter C_DOUT_RST_VAL = "", 2721 parameter C_DOUT_WIDTH = 8, 2722 parameter C_FULL_FLAGS_RST_VAL = 1, 2723 parameter C_HAS_ALMOST_EMPTY = 0, 2724 parameter C_HAS_ALMOST_FULL = 0, 2725 parameter C_HAS_DATA_COUNT = 0, 2726 parameter C_HAS_OVERFLOW = 0, 2727 parameter C_HAS_RD_DATA_COUNT = 0, 2728 parameter C_HAS_RST = 0, 2729 parameter C_HAS_SRST = 0, 2730 parameter C_HAS_UNDERFLOW = 0, 2731 parameter C_HAS_VALID = 0, 2732 parameter C_HAS_WR_ACK = 0, 2733 parameter C_HAS_WR_DATA_COUNT = 0, 2734 parameter C_IMPLEMENTATION_TYPE = 0, 2735 parameter C_MEMORY_TYPE = 1, 2736 parameter C_OVERFLOW_LOW = 0, 2737 parameter C_PRELOAD_LATENCY = 1, 2738 parameter C_PRELOAD_REGS = 0, 2739 parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, 2740 parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, 2741 parameter C_PROG_EMPTY_TYPE = 0, 2742 parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, 2743 parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, 2744 parameter C_PROG_FULL_TYPE = 0, 2745 parameter C_RD_DATA_COUNT_WIDTH = 2, 2746 parameter C_RD_DEPTH = 256, 2747 parameter C_RD_PNTR_WIDTH = 8, 2748 parameter C_UNDERFLOW_LOW = 0, 2749 parameter C_USE_DOUT_RST = 0, 2750 parameter C_USE_EMBEDDED_REG = 0, 2751 parameter C_USE_FWFT_DATA_COUNT = 0, 2752 parameter C_VALID_LOW = 0, 2753 parameter C_WR_ACK_LOW = 0, 2754 parameter C_WR_DATA_COUNT_WIDTH = 2, 2755 parameter C_WR_DEPTH = 256, 2756 parameter C_WR_PNTR_WIDTH = 8, 2757 parameter C_USE_ECC = 0, 2758 parameter C_ENABLE_RST_SYNC = 1, 2759 parameter C_ERROR_INJECTION_TYPE = 0 2760 ) 2761 2762 /************************************************************************** 2763 * Declare Input and Output Ports 2764 *************************************************************************/ 2765 ( 2766 //Inputs 2767 input CLK, 2768 input [C_DIN_WIDTH-1:0] DIN, 2769 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, 2770 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, 2771 input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, 2772 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, 2773 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, 2774 input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, 2775 input RD_EN, 2776 input RST, 2777 input RST_FULL_GEN, 2778 input RST_FULL_FF, 2779 input SRST, 2780 input WR_EN, 2781 input INJECTDBITERR, 2782 input INJECTSBITERR, 2783 2784 //Outputs 2785 output ALMOST_EMPTY, 2786 output ALMOST_FULL, 2787 output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, 2788 output [C_DOUT_WIDTH-1:0] DOUT, 2789 output EMPTY, 2790 output FULL, 2791 output OVERFLOW, 2792 output PROG_EMPTY, 2793 output PROG_FULL, 2794 output VALID, 2795 output UNDERFLOW, 2796 output WR_ACK, 2797 output SBITERR, 2798 output DBITERR 2799 ); 2800 2801 2802 /*************************************************************************** 2803 * Parameters used as constants 2804 **************************************************************************/ 2805 //When RST is present, set FULL reset value to '1'. 2806 //If core has no RST, make sure FULL powers-on as '0'. 2807 //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not 2808 //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. 2809 // Therefore, during SRST, all the FULL flags reset to 0. 2810 parameter C_HAS_FAST_FIFO = 0; 2811 parameter C_FIFO_WR_DEPTH = C_WR_DEPTH; 2812 parameter C_FIFO_RD_DEPTH = C_RD_DEPTH; 2813 2814 /************************************************************************** 2815 * FIFO Contents Tracking and Data Count Calculations 2816 *************************************************************************/ 2817 // Memory which will be used to simulate a FIFO 2818 reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; 2819 // Local parameters used to determine whether to inject ECC error or not 2820 localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; 2821 localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; 2822 localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; 2823 // Array that holds the error injection type (single/double bit error) on 2824 // a specific write operation, which is returned on read to corrupt the 2825 // output data. 2826 reg [1:0] ecc_err[C_WR_DEPTH-1:0]; 2827 2828 //The amount of data stored in the FIFO at any time is given 2829 // by num_bits. 2830 //num_bits is calculated by from the total words in the FIFO. 2831 reg [31:0] num_bits; 2832 2833 //The write pointer - tracks write operations 2834 // (Works opposite to core: wr_ptr is a DOWN counter) 2835 reg [31:0] wr_ptr; 2836 2837 //The write pointer - tracks read operations 2838 // (Works opposite to core: rd_ptr is a DOWN counter) 2839 reg [31:0] rd_ptr; 2840 2841 /************************** 2842 * Data Count 2843 *************************/ 2844 //Amount of data stored in the FIFO scaled to read words 2845 wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; 2846 //num_read_words delayed 1 clock cycle 2847 reg [31:0] num_read_words_q; 2848 2849 //Amount of data stored in the FIFO scaled to write words 2850 wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; 2851 //num_write_words delayed 1 clock cycle 2852 reg [31:0] num_write_words_q; 2853 2854 2855 /************************************************************************** 2856 * Internal Registers and wires 2857 *************************************************************************/ 2858 2859 //Temporary signals used for calculating the model's outputs. These 2860 //are only used in the assign statements immediately following wire, 2861 //parameter, and function declarations. 2862 wire underflow_i; 2863 wire valid_i; 2864 wire valid_out; 2865 2866 //Ideal FIFO signals. These are the raw output of the behavioral model, 2867 //which behaves like an ideal FIFO. 2868 reg [1:0] err_type = 0; 2869 reg [1:0] err_type_d1 = 0; 2870 reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; 2871 reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; 2872 wire [C_DOUT_WIDTH-1:0] ideal_dout_out; 2873 wire fwft_enabled; 2874 reg ideal_wr_ack = 0; 2875 reg ideal_valid = 0; 2876 reg ideal_overflow = 0; 2877 reg ideal_underflow = 0; 2878 reg ideal_full = 0; 2879 reg ideal_empty = 1; 2880 reg ideal_almost_full = 0; 2881 reg ideal_almost_empty = 1; 2882 reg ideal_prog_full = 0; 2883 reg ideal_prog_empty = 1; 2884 2885 //Assorted reg values for delayed versions of signals 2886 reg valid_d1 = 0; 2887 reg prog_full_d = 0; 2888 reg prog_empty_d = 1; 2889 2890 wire rst_i; 2891 wire srst_i; 2892 2893 //Delayed version of RST 2894 reg rst_q; 2895 reg rst_qq; 2896 2897 //user specified value for reseting the size of the fifo 2898 reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; 2899 2900 2901 /**************************************************************************** 2902 * Function Declarations 2903 ***************************************************************************/ 2904 2905 /************************************************************************** 2906 * write_fifo 2907 * This task writes a word to the FIFO memory and updates the 2908 * write pointer. 2909 * FIFO size is relative to write domain. 2910 ***************************************************************************/ 2911 task write_fifo; 2912 reg [1:0] corrupted_data; 2913 begin 2914 memory[wr_ptr] <= DIN; 2915 // Store the type of error injection (double/single) on write 2916 case (C_ERROR_INJECTION_TYPE) 2917 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; 2918 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; 2919 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; 2920 default: ecc_err[wr_ptr] <= 0; 2921 endcase 2922 if (wr_ptr == 0) begin 2923 wr_ptr <= C_WR_DEPTH - 1; 2924 end else begin 2925 wr_ptr <= wr_ptr - 1; 2926 end 2927 end 2928 endtask // write_fifo 2929 2930 /************************************************************************** 2931 * read_fifo 2932 * This task reads a word from the FIFO memory and updates the read 2933 * pointer. It's output is the ideal_dout bus. 2934 * FIFO size is relative to write domain. 2935 ***************************************************************************/ 2936 task read_fifo; 2937 reg [C_DOUT_WIDTH-1:0] tmp_dout; 2938 reg [1:0] tmp_ecc_err; 2939 begin 2940 tmp_dout = memory[rd_ptr][C_DOUT_WIDTH-1:0]; 2941 // Retreive the error injection type. Based on the error injection type 2942 // corrupt the output data. 2943 tmp_ecc_err = ecc_err[rd_ptr]; 2944 if (ENABLE_ERR_INJECTION) begin 2945 if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error 2946 if (C_DOUT_WIDTH == 1) 2947 tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; 2948 else if (C_DOUT_WIDTH == 2) 2949 tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; 2950 else 2951 tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; 2952 end else begin 2953 tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; 2954 end 2955 err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; 2956 end else begin 2957 err_type <= 0; 2958 end 2959 ideal_dout <= tmp_dout; 2960 2961 if (rd_ptr == 0) begin 2962 rd_ptr <= C_RD_DEPTH - 1; 2963 end else begin 2964 rd_ptr <= rd_ptr - 1; 2965 end 2966 end 2967 endtask 2968 2969 /**************************************************************************** 2970 * log2_val 2971 * Returns the 'log2' value for the input value for the supported ratios 2972 ***************************************************************************/ 2973 function [31:0] log2_val; 2974 input [31:0] binary_val; 2975 2976 begin 2977 if (binary_val == 8) begin 2978 log2_val = 3; 2979 end else if (binary_val == 4) begin 2980 log2_val = 2; 2981 end else begin 2982 log2_val = 1; 2983 end 2984 end 2985 endfunction 2986 2987 /**************************************************************************** 2988 * hexstr_conv 2989 * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) 2990 ***************************************************************************/ 2991 function [C_DOUT_WIDTH-1:0] hexstr_conv; 2992 input [(C_DOUT_WIDTH*8)-1:0] def_data; 2993 2994 integer index,i,j; 2995 reg [3:0] bin; 2996 2997 begin 2998 index = 0; 2999 hexstr_conv = 'b0; 3000 for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) 3001 begin 3002 case (def_data[7:0]) 3003 8'b00000000 : 3004 begin 3005 bin = 4'b0000; 3006 i = -1; 3007 end 3008 8'b00110000 : bin = 4'b0000; 3009 8'b00110001 : bin = 4'b0001; 3010 8'b00110010 : bin = 4'b0010; 3011 8'b00110011 : bin = 4'b0011; 3012 8'b00110100 : bin = 4'b0100; 3013 8'b00110101 : bin = 4'b0101; 3014 8'b00110110 : bin = 4'b0110; 3015 8'b00110111 : bin = 4'b0111; 3016 8'b00111000 : bin = 4'b1000; 3017 8'b00111001 : bin = 4'b1001; 3018 8'b01000001 : bin = 4'b1010; 3019 8'b01000010 : bin = 4'b1011; 3020 8'b01000011 : bin = 4'b1100; 3021 8'b01000100 : bin = 4'b1101; 3022 8'b01000101 : bin = 4'b1110; 3023 8'b01000110 : bin = 4'b1111; 3024 8'b01100001 : bin = 4'b1010; 3025 8'b01100010 : bin = 4'b1011; 3026 8'b01100011 : bin = 4'b1100; 3027 8'b01100100 : bin = 4'b1101; 3028 8'b01100101 : bin = 4'b1110; 3029 8'b01100110 : bin = 4'b1111; 3030 default : 3031 begin 3032 bin = 4'bx; 3033 end 3034 endcase 3035 for( j=0; j<4; j=j+1) 3036 begin 3037 if ((index*4)+j < C_DOUT_WIDTH) 3038 begin 3039 hexstr_conv[(index*4)+j] = bin[j]; 3040 end 3041 end 3042 index = index + 1; 3043 def_data = def_data >> 8; 3044 end 3045 end 3046 endfunction 3047 3048 3049 /************************************************************************* 3050 * Initialize Signals for clean power-on simulation 3051 *************************************************************************/ 3052 initial begin 3053 num_bits = 0; 3054 num_read_words_q = 0; 3055 num_write_words_q = 0; 3056 rd_ptr = C_RD_DEPTH -1; 3057 wr_ptr = C_WR_DEPTH -1; 3058 dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); 3059 ideal_dout = dout_reset_val; 3060 err_type = 0; 3061 ideal_wr_ack = 1'b0; 3062 ideal_valid = 1'b0; 3063 valid_d1 = 1'b0; 3064 ideal_overflow = 1'b0; 3065 ideal_underflow = 1'b0; 3066 ideal_full = 1'b0; 3067 ideal_empty = 1'b1; 3068 ideal_almost_full = 1'b0; 3069 ideal_almost_empty = 1'b1; 3070 ideal_prog_full = 1'b0; 3071 ideal_prog_empty = 1'b1; 3072 prog_full_d = 1'b0; 3073 prog_empty_d = 1'b1; 3074 rst_q = 1'b0; 3075 rst_qq = 1'b0; 3076 end 3077 3078 3079 /************************************************************************* 3080 * Connect the module inputs and outputs to the internal signals of the 3081 * behavioral model. 3082 *************************************************************************/ 3083 //Inputs 3084 /* 3085 wire CLK; 3086 wire [C_DIN_WIDTH-1:0] DIN; 3087 wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; 3088 wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; 3089 wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; 3090 wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; 3091 wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; 3092 wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; 3093 wire RD_EN; 3094 wire RST; 3095 wire WR_EN; 3096 */ 3097 3098 //Outputs 3099 generate 3100 if (C_HAS_ALMOST_EMPTY==1) begin : blockAE10 3101 assign ALMOST_EMPTY = ideal_almost_empty; 3102 end 3103 endgenerate 3104 3105 generate 3106 if (C_HAS_ALMOST_FULL==1) begin : blockAF10 3107 assign ALMOST_FULL = ideal_almost_full; 3108 end 3109 endgenerate 3110 3111 //Dout may change behavior based on latency 3112 assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? 3113 1: 0; 3114 assign ideal_dout_out= ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && 3115 (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? 3116 ideal_dout_d1: ideal_dout; 3117 assign DOUT = ideal_dout_out; 3118 3119 // Assign SBITERR and DBITERR based on latency 3120 assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && 3121 ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && 3122 (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? 3123 err_type_d1[0]: err_type[0]; 3124 assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && 3125 ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && 3126 (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? 3127 err_type_d1[1]: err_type[1]; 3128 3129 assign EMPTY = ideal_empty; 3130 assign FULL = ideal_full; 3131 3132 //Overflow may be active-low 3133 generate 3134 if (C_HAS_OVERFLOW==1) begin : blockOF10 3135 assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; 3136 end 3137 endgenerate 3138 3139 assign PROG_EMPTY = ideal_prog_empty; 3140 assign PROG_FULL = ideal_prog_full; 3141 3142 //Valid may change behavior based on latency or active-low 3143 generate 3144 if (C_HAS_VALID==1) begin : blockVL10 3145 assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; 3146 assign valid_out = (C_PRELOAD_LATENCY==2 && 3147 (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? 3148 valid_d1: valid_i; 3149 assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; 3150 end 3151 endgenerate 3152 3153 //Trim data count differently depending on set widths 3154 generate 3155 if ((C_HAS_DATA_COUNT == 1) && 3156 (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH)) begin : blockDC1 3157 always @(num_read_words) 3158 DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH:0]; 3159 end else if (C_HAS_DATA_COUNT == 1) begin : blockDC2 3160 always @(num_read_words) 3161 DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; 3162 end //if 3163 endgenerate 3164 3165 //Underflow may change behavior based on latency or active-low 3166 generate 3167 if (C_HAS_UNDERFLOW==1) begin : blockUF10 3168 assign underflow_i = ideal_underflow; 3169 assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; 3170 end 3171 endgenerate 3172 3173 3174 //Write acknowledge may be active low 3175 generate 3176 if (C_HAS_WR_ACK==1) begin : blockWK10 3177 assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; 3178 end 3179 endgenerate 3180 3181 3182 /***************************************************************************** 3183 * Internal reset logic 3184 ****************************************************************************/ 3185 assign srst_i = C_HAS_SRST ? SRST : 0; 3186 assign rst_i = C_HAS_RST ? RST : 0; 3187 3188 /************************************************************************** 3189 * Assorted registers for delayed versions of signals 3190 **************************************************************************/ 3191 //Capture delayed version of valid 3192 generate 3193 if (C_HAS_VALID==1) begin : blockVL20 3194 always @(posedge CLK or posedge rst_i) begin 3195 if (rst_i == 1'b1) begin 3196 valid_d1 <= #`TCQ 1'b0; 3197 end else begin 3198 if (srst_i) begin 3199 valid_d1 <= #`TCQ 1'b0; 3200 end else begin 3201 valid_d1 <= #`TCQ valid_i; 3202 end 3203 end 3204 end // always @ (posedge CLK or posedge rst_i) 3205 end 3206 endgenerate 3207 3208 3209 // block memory has a synchronous reset 3210 always @(posedge CLK) begin : gen_fifo_blkmemdout_emb 3211 // make it consistent with the core. 3212 if (rst_i || srst_i) begin 3213 // BRAM resets synchronously 3214 if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin 3215 ideal_dout_d1 <= #`TCQ dout_reset_val; 3216 end 3217 end 3218 end //always 3219 3220 reg ram_rd_en_d1 = 1'b0; 3221 //Capture delayed version of dout 3222 always @(posedge CLK or posedge rst_i) begin 3223 if (rst_i == 1'b1) begin 3224 // Reset err_type only if ECC is not selected 3225 if (C_USE_ECC == 0) 3226 err_type_d1 <= #`TCQ 0; 3227 3228 // DRAM and SRAM reset asynchronously 3229 if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) 3230 ideal_dout_d1 <= #`TCQ dout_reset_val; 3231 3232 ram_rd_en_d1 <= #`TCQ 1'b0; 3233 end else begin 3234 ram_rd_en_d1 <= #`TCQ RD_EN & !EMPTY; 3235 if (srst_i) begin 3236 ram_rd_en_d1 <= #`TCQ 1'b0; 3237 // Reset err_type only if ECC is not selected 3238 if (C_USE_ECC == 0) 3239 err_type_d1 <= #`TCQ 0; 3240 // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above 3241 if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) 3242 ideal_dout_d1 <= #`TCQ dout_reset_val; 3243 end else if (ram_rd_en_d1) begin 3244 ideal_dout_d1 <= #`TCQ ideal_dout; 3245 err_type_d1 <= #`TCQ err_type; 3246 end 3247 end 3248 end 3249 3250 /************************************************************************** 3251 * Overflow and Underflow Flag calculation 3252 * (handled separately because they don't support rst) 3253 **************************************************************************/ 3254 generate 3255 if (C_HAS_OVERFLOW==1) begin : blockOF20 3256 always @(posedge CLK) begin 3257 ideal_overflow <= #`TCQ WR_EN & ideal_full; 3258 end 3259 end 3260 endgenerate 3261 3262 generate 3263 if (C_HAS_UNDERFLOW==1) begin : blockUF20 3264 always @(posedge CLK) begin 3265 ideal_underflow <= #`TCQ ideal_empty & RD_EN; 3266 end 3267 end 3268 endgenerate 3269 3270 /************************************************************************* 3271 * Write and Read Logic 3272 ************************************************************************/ 3273 always @(posedge CLK or posedge rst_i) 3274 begin : gen_wr_ack_resp 3275 3276 //Register reset 3277 rst_q <= #`TCQ rst_i; 3278 rst_qq <= #`TCQ rst_q; 3279 3280 end // block: gen_wr_ack_resp 3281 3282 // block memory has a synchronous reset 3283 always @(posedge CLK) begin : gen_fifo_blkmemdout 3284 //Changed the latency of during async reset to '1' instead of '2' to 3285 // make it consistent with the core. 3286 if (rst_i || rst_q || srst_i) begin 3287 // Reset err_type only if ECC is not selected 3288 if (C_USE_ECC == 0 && C_MEMORY_TYPE == 1) 3289 err_type <= #`TCQ 0; 3290 /******Initialize Read Domain Signals*********************************/ 3291 if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin 3292 ideal_dout <= #`TCQ dout_reset_val; 3293 end 3294 end 3295 end //always 3296 3297 // FULL_FLAG_RESET value given for SRST as well. 3298 reg srst_i_d1 = 0; 3299 reg srst_i_d2 = 0; 3300 always @(posedge CLK or posedge RST_FULL_FF) begin : gen_fifo 3301 3302 /****** Reset fifo - Asynchronous Reset**********************************/ 3303 //Changed the latency of during async reset to '1' instead of '2' to 3304 // make it consistent with the core. 3305 if (RST_FULL_FF) begin //v3.2 3306 /******Initialize Generic FIFO constructs*****************************/ 3307 num_bits <= #`TCQ 0; 3308 wr_ptr <= #`TCQ C_WR_DEPTH - 1; 3309 rd_ptr <= #`TCQ C_RD_DEPTH - 1; 3310 num_read_words_q <= #`TCQ 0; 3311 num_write_words_q <= #`TCQ 0; 3312 // Reset err_type only if ECC is not selected 3313 if (C_USE_ECC == 0 && C_MEMORY_TYPE != 1) 3314 err_type <= #`TCQ 0; 3315 3316 3317 /******Initialize Write Domain Signals********************************/ 3318 ideal_wr_ack <= #`TCQ 0; 3319 ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; 3320 ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; 3321 3322 /******Initialize Read Domain Signals*********************************/ 3323 // DRAM and SRAM reset asynchronously 3324 if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin 3325 ideal_dout <= #`TCQ dout_reset_val; 3326 end 3327 ideal_valid <= #`TCQ 1'b0; 3328 ideal_empty <= #`TCQ 1'b1; 3329 ideal_almost_empty <= #`TCQ 1'b1; 3330 3331 end else begin 3332 // Register SRST twice to be consistant with RST behavior 3333 srst_i_d1 <= #`TCQ srst_i; 3334 srst_i_d2 <= #`TCQ srst_i_d1; 3335 if (srst_i) begin 3336 // SRST is available only for Sync BRAM, DRAM and SRAM. 3337 if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin 3338 /******Initialize Generic FIFO constructs***********************/ 3339 num_bits <= #`TCQ 0; 3340 wr_ptr <= #`TCQ C_WR_DEPTH - 1; 3341 rd_ptr <= #`TCQ C_RD_DEPTH - 1; 3342 num_read_words_q <= #`TCQ 0; 3343 num_write_words_q <= #`TCQ 0; 3344 // Reset err_type only if ECC is not selected 3345 if (C_USE_ECC == 0) 3346 err_type <= #`TCQ 0; 3347 3348 /******Initialize Write Domain Signals**************************/ 3349 ideal_wr_ack <= #`TCQ 0; 3350 ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; 3351 ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; 3352 3353 /******Initialize Read Domain Signals***************************/ 3354 //Reset DOUT of Sync DRAM/Shift RAM. Sync BRAM DOUT was reset in the 3355 // above always block. 3356 if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin 3357 ideal_dout <= #`TCQ dout_reset_val; 3358 end 3359 ideal_valid <= #`TCQ 1'b0; 3360 ideal_empty <= #`TCQ 1'b1; 3361 ideal_almost_empty <= #`TCQ 1'b1; 3362 end 3363 3364 end else if ((srst_i_d1 || srst_i_d2) && (C_FULL_FLAGS_RST_VAL == 1)) begin //Hold full flag reset value set during RST/SRST 3365 ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; 3366 ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; 3367 end else begin //normal operating conditions 3368 /********************************************************************/ 3369 // Synchronous FIFO Condition #1 : Writing and not reading 3370 /********************************************************************/ 3371 ideal_valid <= #`TCQ 1'b0; 3372 if (WR_EN & ~RD_EN) begin 3373 3374 /*********************************/ 3375 //If the FIFO is full, do NOT perform the write, 3376 // update flags accordingly 3377 /*********************************/ 3378 if (num_write_words >= C_FIFO_WR_DEPTH) begin 3379 ideal_wr_ack <= #`TCQ 0; 3380 3381 //still full 3382 ideal_full <= #`TCQ 1'b1; 3383 ideal_almost_full <= #`TCQ 1'b1; 3384 3385 //write unsuccessful - do not change contents 3386 3387 // no read attempted 3388 ideal_valid <= #`TCQ 1'b0; 3389 3390 //Not near empty 3391 ideal_empty <= #`TCQ 1'b0; 3392 ideal_almost_empty <= #`TCQ 1'b0; 3393 3394 3395 /*********************************/ 3396 //If the FIFO is reporting FULL 3397 // (Startup condition) 3398 /*********************************/ 3399 end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin 3400 ideal_wr_ack <= #`TCQ 0; 3401 3402 //still full 3403 ideal_full <= #`TCQ 1'b0; 3404 ideal_almost_full <= #`TCQ 1'b0; 3405 3406 //write unsuccessful - do not change contents 3407 3408 // no read attempted 3409 ideal_valid <= #`TCQ 1'b0; 3410 3411 //FIFO EMPTY in this state can not be determined 3412 //ideal_empty <= 1'b0; 3413 //ideal_almost_empty <= 1'b0; 3414 3415 3416 /*********************************/ 3417 //If the FIFO is one from full 3418 /*********************************/ 3419 end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin 3420 //good write 3421 ideal_wr_ack <= #`TCQ 1; 3422 3423 //FIFO is one from FULL and going FULL 3424 ideal_full <= #`TCQ 1'b1; 3425 ideal_almost_full <= #`TCQ 1'b1; 3426 3427 //Add input data 3428 write_fifo; 3429 3430 // no read attempted 3431 ideal_valid <= #`TCQ 1'b0; 3432 3433 //Not near empty 3434 ideal_empty <= #`TCQ 1'b0; 3435 ideal_almost_empty <= #`TCQ 1'b0; 3436 3437 num_bits <= num_bits + C_DIN_WIDTH; 3438 3439 /*********************************/ 3440 //If the FIFO is 2 from full 3441 /*********************************/ 3442 end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin 3443 //good write 3444 ideal_wr_ack <= #`TCQ 1; 3445 3446 //2 from full, and writing, so set almost_full 3447 ideal_full <= #`TCQ 1'b0; 3448 ideal_almost_full <= #`TCQ 1'b1; 3449 3450 //Add input data 3451 write_fifo; 3452 3453 //no read attempted 3454 ideal_valid <= #`TCQ 1'b0; 3455 3456 //Not near empty 3457 ideal_empty <= #`TCQ 1'b0; 3458 ideal_almost_empty <= #`TCQ 1'b0; 3459 3460 num_bits <= #`TCQ num_bits + C_DIN_WIDTH; 3461 3462 /*********************************/ 3463 //If the FIFO is ALMOST EMPTY 3464 /*********************************/ 3465 end else if (num_read_words == 1) begin 3466 //good write 3467 ideal_wr_ack <= #`TCQ 1; 3468 3469 //Not near FULL 3470 ideal_full <= #`TCQ 1'b0; 3471 ideal_almost_full <= #`TCQ 1'b0; 3472 3473 //Add input data 3474 write_fifo; 3475 3476 // no read attempted 3477 ideal_valid <= #`TCQ 1'b0; 3478 3479 //Leaving ALMOST_EMPTY 3480 ideal_empty <= #`TCQ 1'b0; 3481 ideal_almost_empty <= #`TCQ 1'b0; 3482 3483 num_bits <= #`TCQ num_bits + C_DIN_WIDTH; 3484 3485 /*********************************/ 3486 //If the FIFO is EMPTY 3487 /*********************************/ 3488 end else if (num_read_words == 0) begin 3489 // good write 3490 ideal_wr_ack <= #`TCQ 1; 3491 3492 //Not near FULL 3493 ideal_full <= #`TCQ 1'b0; 3494 ideal_almost_full <= #`TCQ 1'b0; 3495 3496 //Add input data 3497 write_fifo; 3498 3499 // no read attempted 3500 ideal_valid <= #`TCQ 1'b0; 3501 3502 //Leaving EMPTY (still ALMOST_EMPTY) 3503 ideal_empty <= #`TCQ 1'b0; 3504 ideal_almost_empty <= #`TCQ 1'b1; 3505 3506 num_bits <= #`TCQ num_bits + C_DIN_WIDTH; 3507 3508 /*********************************/ 3509 //If the FIFO is not near EMPTY or FULL 3510 /*********************************/ 3511 end else begin 3512 // good write 3513 ideal_wr_ack <= #`TCQ 1; 3514 3515 //Not near FULL 3516 ideal_full <= #`TCQ 1'b0; 3517 ideal_almost_full <= #`TCQ 1'b0; 3518 3519 //Add input data 3520 write_fifo; 3521 3522 // no read attempted 3523 ideal_valid <= #`TCQ 1'b0; 3524 3525 //Not near EMPTY 3526 ideal_empty <= #`TCQ 1'b0; 3527 ideal_almost_empty <= #`TCQ 1'b0; 3528 3529 num_bits <= #`TCQ num_bits + C_DIN_WIDTH; 3530 3531 end // average case 3532 3533 3534 /******************************************************************/ 3535 // Synchronous FIFO Condition #2 : Reading and not writing 3536 /******************************************************************/ 3537 end else if (~WR_EN & RD_EN) begin 3538 3539 /*********************************/ 3540 //If the FIFO is EMPTY 3541 /*********************************/ 3542 if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin 3543 //no write attemped 3544 ideal_wr_ack <= #`TCQ 0; 3545 3546 //FIFO is not near FULL 3547 ideal_full <= #`TCQ 1'b0; 3548 ideal_almost_full <= #`TCQ 1'b0; 3549 3550 //Read will fail 3551 ideal_valid <= #`TCQ 1'b0; 3552 3553 //FIFO is still empty 3554 ideal_empty <= #`TCQ 1'b1; 3555 ideal_almost_empty <= #`TCQ 1'b1; 3556 3557 //No read 3558 3559 /*********************************/ 3560 //If the FIFO is ALMOST EMPTY 3561 /*********************************/ 3562 end else if (num_read_words == 1) begin 3563 //no write attempted 3564 ideal_wr_ack <= #`TCQ 0; 3565 3566 //FIFO is not near FULL 3567 ideal_full <= #`TCQ 1'b0; 3568 ideal_almost_full <= #`TCQ 1'b0; 3569 3570 //Read successful 3571 ideal_valid <= #`TCQ 1'b1; 3572 3573 //This read will make FIFO go empty 3574 ideal_empty <= #`TCQ 1'b1; 3575 ideal_almost_empty <= #`TCQ 1'b1; 3576 3577 //Get the data from the FIFO 3578 read_fifo; 3579 num_bits <= #`TCQ num_bits - C_DIN_WIDTH; 3580 3581 3582 /*********************************/ 3583 //If the FIFO is 2 from EMPTY 3584 /*********************************/ 3585 end else if (num_read_words == 2) begin 3586 3587 //no write attempted 3588 ideal_wr_ack <= #`TCQ 0; 3589 3590 //FIFO is not near FULL 3591 ideal_full <= #`TCQ 1'b0; 3592 ideal_almost_full <= #`TCQ 1'b0; 3593 3594 //Read successful 3595 ideal_valid <= #`TCQ 1'b1; 3596 3597 //FIFO is going ALMOST_EMPTY 3598 ideal_empty <= #`TCQ 1'b0; 3599 ideal_almost_empty <= #`TCQ 1'b1; 3600 3601 //Get the data from the FIFO 3602 read_fifo; 3603 num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; 3604 3605 3606 3607 /*********************************/ 3608 //If the FIFO is one from full 3609 /*********************************/ 3610 end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin 3611 3612 //no write attempted 3613 ideal_wr_ack <= #`TCQ 0; 3614 3615 //FIFO is leaving ALMOST FULL 3616 ideal_full <= #`TCQ 1'b0; 3617 ideal_almost_full <= #`TCQ 1'b0; 3618 3619 //Read successful 3620 ideal_valid <= #`TCQ 1'b1; 3621 3622 //Not near empty 3623 ideal_empty <= #`TCQ 1'b0; 3624 ideal_almost_empty <= #`TCQ 1'b0; 3625 3626 //Read from the FIFO 3627 read_fifo; 3628 num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; 3629 3630 3631 /*********************************/ 3632 // FIFO is FULL 3633 /*********************************/ 3634 end else if (num_write_words >= C_FIFO_WR_DEPTH) 3635 begin 3636 //no write attempted 3637 ideal_wr_ack <= #`TCQ 0; 3638 3639 //FIFO is leaving FULL, but is still ALMOST_FULL 3640 ideal_full <= #`TCQ 1'b0; 3641 ideal_almost_full <= #`TCQ 1'b1; 3642 3643 //Read successful 3644 ideal_valid <= #`TCQ 1'b1; 3645 3646 //Not near empty 3647 ideal_empty <= #`TCQ 1'b0; 3648 ideal_almost_empty <= #`TCQ 1'b0; 3649 3650 //Read from the FIFO 3651 read_fifo; 3652 num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; 3653 3654 /*********************************/ 3655 //If the FIFO is not near EMPTY or FULL 3656 /*********************************/ 3657 end else begin 3658 //no write attemped 3659 ideal_wr_ack <= #`TCQ 0; 3660 3661 //Not near empty 3662 ideal_full <= #`TCQ 1'b0; 3663 ideal_almost_full <= #`TCQ 1'b0; 3664 3665 //Read successful 3666 ideal_valid <= #`TCQ 1'b1; 3667 3668 //Not near empty 3669 ideal_empty <= #`TCQ 1'b0; 3670 ideal_almost_empty <= #`TCQ 1'b0; 3671 3672 //Read from the FIFO 3673 read_fifo; 3674 num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; 3675 3676 3677 end // average read 3678 3679 3680 /******************************************************************/ 3681 // Synchronous FIFO Condition #3 : Reading and writing 3682 /******************************************************************/ 3683 end else if (WR_EN & RD_EN) begin 3684 3685 /*********************************/ 3686 // FIFO is FULL 3687 /*********************************/ 3688 if (num_write_words >= C_FIFO_WR_DEPTH) begin 3689 3690 ideal_wr_ack <= #`TCQ 0; 3691 3692 //Read will be successful, so FIFO will leave FULL 3693 ideal_full <= #`TCQ 1'b0; 3694 ideal_almost_full <= #`TCQ 1'b1; 3695 3696 //Read successful 3697 ideal_valid <= #`TCQ 1'b1; 3698 3699 //Not near empty 3700 ideal_empty <= #`TCQ 1'b0; 3701 ideal_almost_empty <= #`TCQ 1'b0; 3702 3703 //Read from the FIFO 3704 read_fifo; 3705 num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; 3706 3707 3708 /*********************************/ 3709 // FIFO is reporting FULL, but it is empty 3710 // (This is a special case, when coming out of RST 3711 /*********************************/ 3712 end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin 3713 3714 ideal_wr_ack <= #`TCQ 0; 3715 3716 //Read will be successful, so FIFO will leave FULL 3717 ideal_full <= #`TCQ 1'b0; 3718 ideal_almost_full <= #`TCQ 1'b0; 3719 3720 //Read unsuccessful 3721 ideal_valid <= #`TCQ 1'b0; 3722 3723 //Report empty condition 3724 ideal_empty <= #`TCQ 1'b1; 3725 ideal_almost_empty <= #`TCQ 1'b1; 3726 3727 //Do not read from empty FIFO 3728 // Read from the FIFO 3729 3730 3731 /*********************************/ 3732 //If the FIFO is one from full 3733 /*********************************/ 3734 end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin 3735 3736 //Write successful 3737 ideal_wr_ack <= #`TCQ 1; 3738 3739 //FIFO will remain ALMOST_FULL 3740 ideal_full <= #`TCQ 1'b0; 3741 ideal_almost_full <= #`TCQ 1'b1; 3742 3743 // put the data into the FIFO 3744 write_fifo; 3745 3746 //Read successful 3747 ideal_valid <= #`TCQ 1'b1; 3748 3749 //Not near empty 3750 ideal_empty <= #`TCQ 1'b0; 3751 ideal_almost_empty <= #`TCQ 1'b0; 3752 3753 //Read from the FIFO 3754 read_fifo; 3755 num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; 3756 3757 /*********************************/ 3758 //If the FIFO is ALMOST EMPTY 3759 /*********************************/ 3760 end else if (num_read_words == 1) begin 3761 3762 //Write successful 3763 ideal_wr_ack <= #`TCQ 1; 3764 3765 // Not near FULL 3766 ideal_full <= #`TCQ 1'b0; 3767 ideal_almost_full <= #`TCQ 1'b0; 3768 3769 // put the data into the FIFO 3770 write_fifo; 3771 3772 //Read successful 3773 ideal_valid <= #`TCQ 1'b1; 3774 3775 //FIFO will stay ALMOST_EMPTY 3776 ideal_empty <= #`TCQ 1'b0; 3777 ideal_almost_empty <= #`TCQ 1'b1; 3778 3779 //Read from the FIFO 3780 read_fifo; 3781 num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; 3782 3783 3784 /*********************************/ 3785 //If the FIFO is EMPTY 3786 /*********************************/ 3787 end else if (num_read_words == 0) begin 3788 3789 //Write successful 3790 ideal_wr_ack <= #`TCQ 1; 3791 3792 // Not near FULL 3793 ideal_full <= #`TCQ 1'b0; 3794 ideal_almost_full <= #`TCQ 1'b0; 3795 3796 // put the data into the FIFO 3797 write_fifo; 3798 3799 //Read will fail 3800 ideal_valid <= #`TCQ 1'b0; 3801 3802 //FIFO will leave EMPTY 3803 ideal_empty <= #`TCQ 1'b0; 3804 ideal_almost_empty <= #`TCQ 1'b1; 3805 3806 // No read 3807 num_bits <= #`TCQ num_bits + C_DIN_WIDTH; 3808 3809 3810 /*********************************/ 3811 //If the FIFO is not near EMPTY or FULL 3812 /*********************************/ 3813 end else begin 3814 3815 //Write successful 3816 ideal_wr_ack <= #`TCQ 1; 3817 3818 // Not near FULL 3819 ideal_full <= #`TCQ 1'b0; 3820 ideal_almost_full <= #`TCQ 1'b0; 3821 3822 // put the data into the FIFO 3823 write_fifo; 3824 3825 //Read successful 3826 ideal_valid <= #`TCQ 1'b1; 3827 3828 // Not near EMPTY 3829 ideal_empty <= #`TCQ 1'b0; 3830 ideal_almost_empty <= #`TCQ 1'b0; 3831 3832 //Read from the FIFO 3833 read_fifo; 3834 num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; 3835 3836 end // average case 3837 3838 /******************************************************************/ 3839 // Synchronous FIFO Condition #4 : Not reading or writing 3840 /******************************************************************/ 3841 end else begin 3842 3843 /*********************************/ 3844 // FIFO is FULL 3845 /*********************************/ 3846 if (num_write_words >= C_FIFO_WR_DEPTH) begin 3847 3848 //No write 3849 ideal_wr_ack <= #`TCQ 0; 3850 ideal_full <= #`TCQ 1'b1; 3851 ideal_almost_full <= #`TCQ 1'b1; 3852 3853 //No read 3854 ideal_valid <= #`TCQ 1'b0; 3855 ideal_empty <= #`TCQ 1'b0; 3856 ideal_almost_empty <= #`TCQ 1'b0; 3857 3858 //No change to memory 3859 3860 /*********************************/ 3861 //If the FIFO is one from full 3862 /*********************************/ 3863 end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin 3864 3865 //No write 3866 ideal_wr_ack <= #`TCQ 0; 3867 ideal_full <= #`TCQ 1'b0; 3868 ideal_almost_full <= #`TCQ 1'b1; 3869 3870 //No read 3871 ideal_valid <= #`TCQ 1'b0; 3872 ideal_empty <= #`TCQ 1'b0; 3873 ideal_almost_empty <= #`TCQ 1'b0; 3874 3875 //No change to memory 3876 3877 /*********************************/ 3878 //If the FIFO is ALMOST EMPTY 3879 /*********************************/ 3880 end else if (num_read_words == 1) begin 3881 //No write 3882 ideal_wr_ack <= #`TCQ 0; 3883 ideal_full <= #`TCQ 1'b0; 3884 ideal_almost_full <= #`TCQ 1'b0; 3885 3886 //No read 3887 ideal_valid <= #`TCQ 1'b0; 3888 ideal_empty <= #`TCQ 1'b0; 3889 ideal_almost_empty <= #`TCQ 1'b1; 3890 3891 //No change to memory 3892 3893 end // almost empty 3894 3895 3896 /*********************************/ 3897 //If the FIFO is EMPTY 3898 /*********************************/ 3899 else if (num_read_words == 0) 3900 begin 3901 //No write 3902 ideal_wr_ack <= #`TCQ 0; 3903 ideal_full <= #`TCQ 1'b0; 3904 ideal_almost_full <= #`TCQ 1'b0; 3905 3906 //No read 3907 ideal_valid <= #`TCQ 1'b0; 3908 ideal_empty <= #`TCQ 1'b1; 3909 ideal_almost_empty <= #`TCQ 1'b1; 3910 3911 //No change to memory 3912 3913 /*********************************/ 3914 //If the FIFO is not near EMPTY or FULL 3915 /*********************************/ 3916 end else begin 3917 3918 //No write 3919 ideal_wr_ack <= #`TCQ 0; 3920 ideal_full <= #`TCQ 1'b0; 3921 ideal_almost_full <= #`TCQ 1'b0; 3922 3923 //No read 3924 ideal_valid <= #`TCQ 1'b0; 3925 ideal_empty <= #`TCQ 1'b0; 3926 ideal_almost_empty <= #`TCQ 1'b0; 3927 3928 //No change to memory 3929 3930 end // average case 3931 3932 end // neither reading or writing 3933 3934 num_read_words_q <= #`TCQ num_read_words; 3935 num_write_words_q <= #`TCQ num_write_words; 3936 3937 end //normal operating conditions 3938 end 3939 3940 end // block: gen_fifo 3941 3942 3943 always @(posedge CLK or posedge RST_FULL_FF) begin : gen_fifo_p 3944 3945 /****** Reset fifo - Async Reset****************************************/ 3946 //The latency of de-assertion of the flags is reduced by 1 to be 3947 // consistent with the core. 3948 if (RST_FULL_FF) begin 3949 ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; 3950 ideal_prog_empty <= #`TCQ 1'b1; 3951 prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; 3952 prog_empty_d <= #`TCQ 1'b1; 3953 3954 end else begin 3955 if (srst_i) begin 3956 //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. 3957 if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin 3958 ideal_prog_empty <= #`TCQ 1'b1; 3959 prog_empty_d <= #`TCQ 1'b1; 3960 ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; 3961 prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; 3962 end 3963 end else if ((srst_i_d1 || srst_i_d2) && (C_FULL_FLAGS_RST_VAL == 1)) begin 3964 ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; 3965 prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; 3966 end else begin 3967 3968 /*************************************************************** 3969 * Programmable FULL flags 3970 ****************************************************************/ 3971 //calculation for standard fifo and latency =2 3972 if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin 3973 //Single constant threshold 3974 if (C_PROG_FULL_TYPE == 1) begin 3975 if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) 3976 && WR_EN && !RD_EN) begin 3977 prog_full_d <= #`TCQ 1'b1; 3978 end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) 3979 && RD_EN && !WR_EN) || (RST_FULL_GEN)) begin 3980 prog_full_d <= #`TCQ 1'b0; 3981 end 3982 3983 //Dual constant thresholds 3984 end else if (C_PROG_FULL_TYPE == 2) begin 3985 if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) 3986 && WR_EN && !RD_EN) begin 3987 prog_full_d <= #`TCQ 1'b1; 3988 end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) 3989 && RD_EN && !WR_EN) begin 3990 prog_full_d <= #`TCQ 1'b0; 3991 end 3992 3993 //Single input threshold 3994 end else if (C_PROG_FULL_TYPE == 3) begin 3995 if ((num_write_words == PROG_FULL_THRESH-1) 3996 && WR_EN && !RD_EN) begin 3997 prog_full_d <= #`TCQ 1'b1; 3998 end else if ((num_write_words == PROG_FULL_THRESH) 3999 && !WR_EN && RD_EN) begin 4000 prog_full_d <= #`TCQ 1'b0; 4001 end else if (num_write_words >= PROG_FULL_THRESH) begin 4002 prog_full_d <= #`TCQ 1'b1; 4003 end else if (num_write_words < PROG_FULL_THRESH) begin 4004 prog_full_d <= #`TCQ 1'b0; 4005 end 4006 4007 //Dual input thresholds 4008 end else begin 4009 if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) 4010 && WR_EN && !RD_EN) begin 4011 prog_full_d <= #`TCQ 1'b1; 4012 end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) 4013 && !WR_EN && RD_EN)begin 4014 prog_full_d <= #`TCQ 1'b0; 4015 end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin 4016 prog_full_d <= #`TCQ 1'b1; 4017 end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin 4018 prog_full_d <= #`TCQ 1'b0; 4019 end 4020 end 4021 end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) 4022 4023 4024 //calculation for FWFT fifo 4025 if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin 4026 if (C_PROG_FULL_TYPE == 1) begin 4027 if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) 4028 && WR_EN && !RD_EN) begin 4029 prog_full_d <= #`TCQ 1'b1; 4030 end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL - 2) 4031 && RD_EN && !WR_EN) || (RST_FULL_GEN)) begin 4032 prog_full_d <= #`TCQ 1'b0; 4033 end 4034 4035 //Dual constant thresholds 4036 end else if (C_PROG_FULL_TYPE == 2) begin 4037 if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) 4038 && WR_EN && !RD_EN) begin 4039 prog_full_d <= #`TCQ 1'b1; 4040 end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL - 2) 4041 && RD_EN && !WR_EN) begin 4042 prog_full_d <= #`TCQ 1'b0; 4043 end 4044 4045 //Single input threshold 4046 end else if (C_PROG_FULL_TYPE == 3) begin 4047 if ((num_write_words == PROG_FULL_THRESH-1 - 2) 4048 && WR_EN && !RD_EN) begin 4049 prog_full_d <= #`TCQ 1'b1; 4050 end else if ((num_write_words == PROG_FULL_THRESH - 2) 4051 && !WR_EN && RD_EN) begin 4052 prog_full_d <= #`TCQ 1'b0; 4053 end else if (num_write_words >= PROG_FULL_THRESH - 2) begin 4054 prog_full_d <= #`TCQ 1'b1; 4055 end else if (num_write_words < PROG_FULL_THRESH - 2) begin 4056 prog_full_d <= #`TCQ 1'b0; 4057 end 4058 4059 //Dual input thresholds 4060 end else begin 4061 if ((num_write_words == PROG_FULL_THRESH_ASSERT-1 - 2) 4062 && WR_EN && !RD_EN) begin 4063 prog_full_d <= #`TCQ 1'b1; 4064 end else if ((num_write_words == PROG_FULL_THRESH_NEGATE - 2) 4065 && !WR_EN && RD_EN)begin 4066 prog_full_d <= #`TCQ 1'b0; 4067 end else if (num_write_words >= PROG_FULL_THRESH_ASSERT - 2) begin 4068 prog_full_d <= #`TCQ 1'b1; 4069 end else if (num_write_words < PROG_FULL_THRESH_NEGATE - 2) begin 4070 prog_full_d <= #`TCQ 1'b0; 4071 end 4072 end 4073 end // (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) 4074 4075 /***************************************************************** 4076 * Programmable EMPTY flags 4077 ****************************************************************/ 4078 //calculation for standard fifo and latency = 2 4079 if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin 4080 //Single constant threshold 4081 if (C_PROG_EMPTY_TYPE == 1) begin 4082 if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) 4083 && RD_EN && !WR_EN) begin 4084 prog_empty_d <= #`TCQ 1'b1; 4085 end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) 4086 && WR_EN && !RD_EN) begin 4087 prog_empty_d <= #`TCQ 1'b0; 4088 end 4089 //Dual constant thresholds 4090 end else if (C_PROG_EMPTY_TYPE == 2) begin 4091 if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) 4092 && RD_EN && !WR_EN) begin 4093 prog_empty_d <= #`TCQ 1'b1; 4094 end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) 4095 && !RD_EN && WR_EN) begin 4096 prog_empty_d <= #`TCQ 1'b0; 4097 end 4098 4099 //Single input threshold 4100 end else if (C_PROG_EMPTY_TYPE == 3) begin 4101 if ((num_read_words == PROG_EMPTY_THRESH+1) 4102 && RD_EN && !WR_EN) begin 4103 prog_empty_d <= #`TCQ 1'b1; 4104 end else if ((num_read_words == PROG_EMPTY_THRESH) 4105 && !RD_EN && WR_EN) begin 4106 prog_empty_d <= #`TCQ 1'b0; 4107 end else if (num_read_words <= PROG_EMPTY_THRESH) begin 4108 prog_empty_d <= #`TCQ 1'b1; 4109 end else if (num_read_words > PROG_EMPTY_THRESH)begin 4110 prog_empty_d <= #`TCQ 1'b0; 4111 end 4112 4113 //Dual input thresholds 4114 end else begin 4115 if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin 4116 prog_empty_d <= #`TCQ 1'b1; 4117 end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) 4118 && RD_EN && !WR_EN) begin 4119 prog_empty_d <= #`TCQ 1'b1; 4120 end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin 4121 prog_empty_d <= #`TCQ 1'b0; 4122 end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) 4123 && !RD_EN && WR_EN) begin 4124 prog_empty_d <= #`TCQ 1'b0; 4125 end 4126 end 4127 end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) 4128 4129 //calculation for FWFT fifo 4130 if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin 4131 //Single constant threshold 4132 if (C_PROG_EMPTY_TYPE == 1) begin 4133 if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) 4134 && RD_EN && !WR_EN) begin 4135 prog_empty_d <= #`TCQ 1'b1; 4136 end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL - 2) 4137 && WR_EN && !RD_EN) begin 4138 prog_empty_d <= #`TCQ 1'b0; 4139 end 4140 //Dual constant thresholds 4141 end else if (C_PROG_EMPTY_TYPE == 2) begin 4142 if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) 4143 && RD_EN && !WR_EN) begin 4144 prog_empty_d <= #`TCQ 1'b1; 4145 end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL - 2) 4146 && !RD_EN && WR_EN) begin 4147 prog_empty_d <= #`TCQ 1'b0; 4148 end 4149 4150 //Single input threshold 4151 end else if (C_PROG_EMPTY_TYPE == 3) begin 4152 if ((num_read_words == PROG_EMPTY_THRESH+1 - 2) 4153 && RD_EN && !WR_EN) begin 4154 prog_empty_d <= #`TCQ 1'b1; 4155 end else if ((num_read_words == PROG_EMPTY_THRESH - 2) 4156 && !RD_EN && WR_EN) begin 4157 prog_empty_d <= #`TCQ 1'b0; 4158 end else if (num_read_words <= PROG_EMPTY_THRESH - 2) begin 4159 prog_empty_d <= #`TCQ 1'b1; 4160 end else if (num_read_words > PROG_EMPTY_THRESH - 2)begin 4161 prog_empty_d <= #`TCQ 1'b0; 4162 end 4163 4164 //Dual input thresholds 4165 end else begin 4166 if (num_read_words <= PROG_EMPTY_THRESH_ASSERT - 2) begin 4167 prog_empty_d <= #`TCQ 1'b1; 4168 end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1 - 2) 4169 && RD_EN && !WR_EN) begin 4170 prog_empty_d <= #`TCQ 1'b1; 4171 end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE - 2)begin 4172 prog_empty_d <= #`TCQ 1'b0; 4173 end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE - 2) 4174 && !RD_EN && WR_EN) begin 4175 prog_empty_d <= #`TCQ 1'b0; 4176 end 4177 end 4178 end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) 4179 4180 ideal_prog_empty <= prog_empty_d; 4181 if (RST_FULL_GEN) begin 4182 ideal_prog_full <= #`TCQ 1'b0; 4183 prog_full_d <= #`TCQ 1'b0; 4184 end else begin 4185 ideal_prog_full <= #`TCQ prog_full_d; 4186 end 4187 4188 end //if (srst_i) begin 4189 end //if (rst_i) begin 4190 end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p 4191endmodule // fifo_generator_v6_1_bhv_ver_ss 4192 4193 4194 4195/************************************************************************** 4196 * First-Word Fall-Through module (preload 0) 4197 **************************************************************************/ 4198module fifo_generator_v6_1_bhv_ver_preload0 4199 ( 4200 RD_CLK, 4201 RD_RST, 4202 SRST, 4203 RD_EN, 4204 FIFOEMPTY, 4205 FIFODATA, 4206 FIFOSBITERR, 4207 FIFODBITERR, 4208 USERDATA, 4209 USERVALID, 4210 USERUNDERFLOW, 4211 USEREMPTY, 4212 USERALMOSTEMPTY, 4213 RAMVALID, 4214 FIFORDEN, 4215 USERSBITERR, 4216 USERDBITERR 4217 ); 4218 4219 parameter C_DOUT_RST_VAL = ""; 4220 parameter C_DOUT_WIDTH = 8; 4221 parameter C_HAS_RST = 0; 4222 parameter C_ENABLE_RST_SYNC = 0; 4223 parameter C_HAS_SRST = 0; 4224 parameter C_USE_DOUT_RST = 0; 4225 parameter C_USE_ECC = 0; 4226 parameter C_USERVALID_LOW = 0; 4227 parameter C_USERUNDERFLOW_LOW = 0; 4228 parameter C_MEMORY_TYPE = 0; 4229 4230 //Inputs 4231 input RD_CLK; 4232 input RD_RST; 4233 input SRST; 4234 input RD_EN; 4235 input FIFOEMPTY; 4236 input [C_DOUT_WIDTH-1:0] FIFODATA; 4237 input FIFOSBITERR; 4238 input FIFODBITERR; 4239 4240 //Outputs 4241 output [C_DOUT_WIDTH-1:0] USERDATA; 4242 output USERVALID; 4243 output USERUNDERFLOW; 4244 output USEREMPTY; 4245 output USERALMOSTEMPTY; 4246 output RAMVALID; 4247 output FIFORDEN; 4248 output USERSBITERR; 4249 output USERDBITERR; 4250 4251 //Inputs 4252 wire RD_CLK; 4253 wire RD_RST; 4254 wire RD_EN; 4255 wire FIFOEMPTY; 4256 wire [C_DOUT_WIDTH-1:0] FIFODATA; 4257 wire FIFOSBITERR; 4258 wire FIFODBITERR; 4259 4260 //Outputs 4261 reg [C_DOUT_WIDTH-1:0] USERDATA; 4262 wire USERVALID; 4263 wire USERUNDERFLOW; 4264 wire USEREMPTY; 4265 wire USERALMOSTEMPTY; 4266 wire RAMVALID; 4267 wire FIFORDEN; 4268 reg USERSBITERR; 4269 reg USERDBITERR; 4270 4271 //Internal signals 4272 wire preloadstage1; 4273 wire preloadstage2; 4274 reg ram_valid_i; 4275 reg read_data_valid_i; 4276 wire ram_regout_en; 4277 wire ram_rd_en; 4278 reg empty_i = 1'b1; 4279 reg empty_q = 1'b1; 4280 reg rd_en_q = 1'b0; 4281 reg almost_empty_i = 1'b1; 4282 reg almost_empty_q = 1'b1; 4283 wire rd_rst_i; 4284 wire srst_i; 4285 4286 4287/************************************************************************* 4288* FUNCTIONS 4289*************************************************************************/ 4290 4291 /************************************************************************* 4292 * hexstr_conv 4293 * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) 4294 ***********************************************************************/ 4295 function [C_DOUT_WIDTH-1:0] hexstr_conv; 4296 input [(C_DOUT_WIDTH*8)-1:0] def_data; 4297 4298 integer index,i,j; 4299 reg [3:0] bin; 4300 4301 begin 4302 index = 0; 4303 hexstr_conv = 'b0; 4304 for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) 4305 begin 4306 case (def_data[7:0]) 4307 8'b00000000 : 4308 begin 4309 bin = 4'b0000; 4310 i = -1; 4311 end 4312 8'b00110000 : bin = 4'b0000; 4313 8'b00110001 : bin = 4'b0001; 4314 8'b00110010 : bin = 4'b0010; 4315 8'b00110011 : bin = 4'b0011; 4316 8'b00110100 : bin = 4'b0100; 4317 8'b00110101 : bin = 4'b0101; 4318 8'b00110110 : bin = 4'b0110; 4319 8'b00110111 : bin = 4'b0111; 4320 8'b00111000 : bin = 4'b1000; 4321 8'b00111001 : bin = 4'b1001; 4322 8'b01000001 : bin = 4'b1010; 4323 8'b01000010 : bin = 4'b1011; 4324 8'b01000011 : bin = 4'b1100; 4325 8'b01000100 : bin = 4'b1101; 4326 8'b01000101 : bin = 4'b1110; 4327 8'b01000110 : bin = 4'b1111; 4328 8'b01100001 : bin = 4'b1010; 4329 8'b01100010 : bin = 4'b1011; 4330 8'b01100011 : bin = 4'b1100; 4331 8'b01100100 : bin = 4'b1101; 4332 8'b01100101 : bin = 4'b1110; 4333 8'b01100110 : bin = 4'b1111; 4334 default : 4335 begin 4336 bin = 4'bx; 4337 end 4338 endcase 4339 for( j=0; j<4; j=j+1) 4340 begin 4341 if ((index*4)+j < C_DOUT_WIDTH) 4342 begin 4343 hexstr_conv[(index*4)+j] = bin[j]; 4344 end 4345 end 4346 index = index + 1; 4347 def_data = def_data >> 8; 4348 end 4349 end 4350 endfunction 4351 4352 4353 //************************************************************************* 4354 // Set power-on states for regs 4355 //************************************************************************* 4356 initial begin 4357 ram_valid_i = 1'b0; 4358 read_data_valid_i = 1'b0; 4359 USERDATA = hexstr_conv(C_DOUT_RST_VAL); 4360 USERSBITERR = 1'b0; 4361 USERDBITERR = 1'b0; 4362 end //initial 4363 4364 //*************************************************************************** 4365 // connect up optional reset 4366 //*************************************************************************** 4367 assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0; 4368 assign srst_i = C_HAS_SRST ? SRST : 0; 4369 4370 4371 //*************************************************************************** 4372 // preloadstage2 indicates that stage2 needs to be updated. This is true 4373 // whenever read_data_valid is false, and RAM_valid is true. 4374 //*************************************************************************** 4375 assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); 4376 4377 //*************************************************************************** 4378 // preloadstage1 indicates that stage1 needs to be updated. This is true 4379 // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is 4380 // false (indicating that Stage1 needs updating), or preloadstage2 is active 4381 // (indicating that Stage2 is going to update, so Stage1, therefore, must 4382 // also be updated to keep it valid. 4383 //*************************************************************************** 4384 assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); 4385 4386 //*************************************************************************** 4387 // Calculate RAM_REGOUT_EN 4388 // The output registers are controlled by the ram_regout_en signal. 4389 // These registers should be updated either when the output in Stage2 is 4390 // invalid (preloadstage2), OR when the user is reading, in which case the 4391 // Stage2 value will go invalid unless it is replenished. 4392 //*************************************************************************** 4393 assign ram_regout_en = preloadstage2; 4394 4395 //*************************************************************************** 4396 // Calculate RAM_RD_EN 4397 // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to 4398 // update the value in Stage1. 4399 // One case when this happens is when preloadstage1=true, which indicates 4400 // that the data in Stage1 or Stage2 is invalid, and needs to automatically 4401 // be updated. 4402 // The other case is when the user is reading from the FIFO, which 4403 // guarantees that Stage1 or Stage2 will be invalid on the next clock 4404 // cycle, unless it is replinished by data from the memory. So, as long 4405 // as the RAM has data in it, a read of the RAM should occur. 4406 //*************************************************************************** 4407 assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; 4408 4409 //*************************************************************************** 4410 // Calculate RAMVALID_P0_OUT 4411 // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. 4412 // 4413 // If the RAM is being read from on this clock cycle (ram_rd_en=1), then 4414 // RAMVALID_P0_OUT is certainly going to be true. 4415 // If the RAM is not being read from, but the output registers are being 4416 // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, 4417 // therefore causing RAMVALID_P0_OUT to be false. 4418 // Otherwise, RAMVALID_P0_OUT will remain unchanged. 4419 //*************************************************************************** 4420 // PROCESS regout_valid 4421 always @ (posedge RD_CLK or posedge rd_rst_i) begin 4422 if (rd_rst_i) begin 4423 // asynchronous reset (active high) 4424 ram_valid_i <= #`TCQ 1'b0; 4425 end else begin 4426 if (srst_i) begin 4427 // synchronous reset (active high) 4428 ram_valid_i <= #`TCQ 1'b0; 4429 end else begin 4430 if (ram_rd_en == 1'b1) begin 4431 ram_valid_i <= #`TCQ 1'b1; 4432 end else begin 4433 if (ram_regout_en == 1'b1) 4434 ram_valid_i <= #`TCQ 1'b0; 4435 else 4436 ram_valid_i <= #`TCQ ram_valid_i; 4437 end 4438 end //srst_i 4439 end //rd_rst_i 4440 end //always 4441 4442 //*************************************************************************** 4443 // Calculate READ_DATA_VALID 4444 // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. 4445 // Stage2 has valid data whenever Stage1 had valid data and 4446 // ram_regout_en_i=1, such that the data in Stage1 is propogated 4447 // into Stage2. 4448 //*************************************************************************** 4449 always @ (posedge RD_CLK or posedge rd_rst_i) begin 4450 if (rd_rst_i) 4451 read_data_valid_i <= #`TCQ 1'b0; 4452 else if (srst_i) 4453 read_data_valid_i <= #`TCQ 1'b0; 4454 else 4455 read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN); 4456 end //always 4457 4458 4459 //************************************************************************** 4460 // Calculate EMPTY 4461 // Defined as the inverse of READ_DATA_VALID 4462 // 4463 // Description: 4464 // 4465 // If read_data_valid_i indicates that the output is not valid, 4466 // and there is no valid data on the output of the ram to preload it 4467 // with, then we will report empty. 4468 // 4469 // If there is no valid data on the output of the ram and we are 4470 // reading, then the FIFO will go empty. 4471 // 4472 //************************************************************************** 4473 always @ (posedge RD_CLK or posedge rd_rst_i) begin 4474 if (rd_rst_i) begin 4475 // asynchronous reset (active high) 4476 empty_i <= #`TCQ 1'b1; 4477 end else begin 4478 if (srst_i) begin 4479 // synchronous reset (active high) 4480 empty_i <= #`TCQ 1'b1; 4481 end else begin 4482 // rising clock edge 4483 empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); 4484 end 4485 end 4486 end //always 4487 4488 // Register RD_EN from user to calculate USERUNDERFLOW. 4489 // Register empty_i to calculate USERUNDERFLOW. 4490 always @ (posedge RD_CLK) begin 4491 rd_en_q <= #`TCQ RD_EN; 4492 empty_q <= #`TCQ empty_i; 4493 end //always 4494 4495 4496 //*************************************************************************** 4497 // Calculate user_almost_empty 4498 // user_almost_empty is defined such that, unless more words are written 4499 // to the FIFO, the next read will cause the FIFO to go EMPTY. 4500 // 4501 // In most cases, whenever the output registers are updated (due to a user 4502 // read or a preload condition), then user_almost_empty will update to 4503 // whatever RAM_EMPTY is. 4504 // 4505 // The exception is when the output is valid, the user is not reading, and 4506 // Stage1 is not empty. In this condition, Stage1 will be preloaded from the 4507 // memory, so we need to make sure user_almost_empty deasserts properly under 4508 // this condition. 4509 //*************************************************************************** 4510 always @ (posedge RD_CLK or posedge rd_rst_i) 4511 begin 4512 if (rd_rst_i) begin // asynchronous reset (active high) 4513 almost_empty_i <= #`TCQ 1'b1; 4514 almost_empty_q <= #`TCQ 1'b1; 4515 end else begin // rising clock edge 4516 if (srst_i) begin // synchronous reset (active high) 4517 almost_empty_i <= #`TCQ 1'b1; 4518 almost_empty_q <= #`TCQ 1'b1; 4519 end else begin 4520 if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin 4521 almost_empty_i <= #`TCQ FIFOEMPTY; 4522 end 4523 almost_empty_q <= #`TCQ empty_i; 4524 end 4525 end 4526 end //always 4527 4528 4529 assign USEREMPTY = empty_i; 4530 assign USERALMOSTEMPTY = almost_empty_i; 4531 assign FIFORDEN = ram_rd_en; 4532 assign RAMVALID = ram_valid_i; 4533 assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; 4534 assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; 4535 4536 // BRAM resets synchronously 4537 always @ (posedge RD_CLK) 4538 begin 4539 if (rd_rst_i || srst_i) begin 4540 if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) 4541 USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); 4542 end 4543 end //always 4544 4545 4546 always @ (posedge RD_CLK or posedge rd_rst_i) 4547 begin 4548 if (rd_rst_i) begin //asynchronous reset (active high) 4549 if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF 4550 USERSBITERR <= #`TCQ 0; 4551 USERDBITERR <= #`TCQ 0; 4552 end 4553 // DRAM resets asynchronously 4554 if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) //asynchronous reset (active high) 4555 USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); 4556 end else begin // rising clock edge 4557 if (srst_i) begin 4558 if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF 4559 USERSBITERR <= #`TCQ 0; 4560 USERDBITERR <= #`TCQ 0; 4561 end 4562 if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) 4563 USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); 4564 end else begin 4565 if (ram_regout_en) begin 4566 USERDATA <= #`TCQ FIFODATA; 4567 USERSBITERR <= #`TCQ FIFOSBITERR; 4568 USERDBITERR <= #`TCQ FIFODBITERR; 4569 end 4570 end 4571 end 4572 end //always 4573 4574endmodule 4575 4576