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Searched refs:gpt1_base (Results 1 – 25 of 70) sorted by relevance

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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/omap3/
H A Dclock.c46 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
74 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
75 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
86 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
90 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/omap3/
H A Dclock.c46 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
74 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
75 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
86 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
90 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/omap3/
H A Dclock.c46 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
74 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
75 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
86 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
90 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/omap3/
H A Dclock.c46 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
74 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
75 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
86 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
90 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/omap3/
H A Dclock.c46 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
74 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
75 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
86 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
90 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/omap3/
H A Dclock.c46 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
74 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
75 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
86 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
90 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/arm/cpu/arm_cortexa8/omap3/
H A Dclock.c46 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
74 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
75 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
86 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
90 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-omap2/omap3/
H A Dclock.c32 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
55 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
56 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
67 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
71 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-omap2/omap3/
H A Dclock.c32 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
55 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
56 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
67 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
71 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-omap2/omap3/
H A Dclock.c31 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
54 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
55 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
66 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
70 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-omap2/omap3/
H A Dclock.c31 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
54 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
55 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
66 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
70 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-omap2/omap3/
H A Dclock.c31 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
54 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
55 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
66 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
70 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-omap2/omap3/
H A Dclock.c31 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
54 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
55 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
66 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
70 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-omap2/omap3/
H A Dclock.c31 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
54 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
55 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
66 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
70 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-omap2/omap3/
H A Dclock.c31 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
54 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
55 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
66 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
70 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-omap2/omap3/
H A Dclock.c31 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
54 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
55 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
66 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
70 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-omap2/omap3/
H A Dclock.c31 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
54 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
55 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
66 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
70 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-omap2/omap3/
H A Dclock.c31 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
54 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
55 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
66 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
70 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-omap2/omap3/
H A Dclock.c31 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
54 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
55 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
66 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
70 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-omap2/omap3/
H A Dclock.c31 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
54 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
55 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
66 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
70 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-omap2/omap3/
H A Dclock.c31 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
54 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
55 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
66 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
70 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-omap2/omap3/
H A Dclock.c31 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
54 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
55 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
66 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
70 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-omap2/omap3/
H A Dclock.c32 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
55 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
56 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
67 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
71 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-omap2/omap3/
H A Dclock.c32 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
55 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
56 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
67 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
71 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-omap2/omap3/
H A Dclock.c31 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1; in get_osc_clk_speed() local
54 writel(0, &gpt1_base->tldr); /* start counting at 0 */ in get_osc_clk_speed()
55 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */ in get_osc_clk_speed()
66 cstart = readl(&gpt1_base->tcrr); in get_osc_clk_speed()
70 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */ in get_osc_clk_speed()

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